PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 255

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

FIGURE 23-2:
23.4
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro
divided on binary boundaries into individual blocks,
each of which has three separate code protection bits
associated with it:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
The code protection bits are located in Configuration
Registers 5L through 7H. Their locations within the
registers are summarized in Table 23-3.
TABLE 23-3:
 2004 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
Note 1:
(INTCON<1>)
(INTCON<7>)
Note
INSTRUCTION FLOW
Instruction
Instruction
Executed
INTF flag
GIEH bit
CLKO
Fetched
INT pin
OSC1
File Name
Program Verification and
Code Protection
1:
2:
3:
4:
®
PC
(4)
Unimplemented in PIC18FX520 and PIC18FX620 devices.
devices. The user program memory is
XT, HS or LP Oscillator mode assumed.
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
T
CLKO is not available in these oscillator modes, but shown here for timing reference.
OST
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L EBTR7
CONFIG7H
Inst(PC) = Sleep
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC - 1)
= 1024 T
PIC18F6520/8520/6620/8620/6720/8720
SUMMARY OF CODE PROTECTION REGISTERS
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
(drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
WRT7
CP7
WRTD
Bit 7
CPD
Inst(PC + 2)
—
Sleep
PC+2
(1)
(1)
(1)
EBTR6
WRT6
EBTRB
CP6
WRTB
Bit 6
CPB
Processor in
(1)
Sleep
(1)
(1)
PC+4
EBTR5
WRT5
CP5
WRTC
Bit 5
T
—
—
OST
(1)
(2)
(1)
(1)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
EBTR4
Inst(PC + 4)
Inst(PC + 2)
WRT4
CP4
In the PIC18FXX20 family, the block size varies with
the size of the user program memory. For PIC18FX520
devices, program memory is divided into four blocks of
8 Kbytes each. The first block is further divided into a
boot block of 2 Kbytes and a second block (Block 0) of
6 Kbytes, for a total of five blocks. The organization of
the blocks and their associated code protection bits are
shown in Figure 23-3.
For PIC18FX620 and PIC18FX720 devices, program
memory is divided into blocks of 16 Kbytes. The first
block is further divided into a boot block of 512 bytes
and a second block (Block 0) of 15.5 Kbytes, for a total
of nine blocks. This produces five blocks for 64-Kbyte
devices and nine for 128-Kbyte devices. The organiza-
tion of the blocks and their associated code protection
bits are shown in Figure 23-4.
Bit 4
PC+4
—
—
—
(1)
(1)
(1)
Interrupt Latency
EBTR3
WRT3
Dummy Cycle
Bit 3
CP3
—
—
—
PC + 4
(1,2)
EBTR2
WRT2
Bit 2
CP2
(3)
—
—
—
Dummy Cycle
Inst(0008h)
0008h
EBTR1
WRT1
Bit 1
CP1
DS39609B-page 253
—
—
—
Inst(000Ah)
Inst(0008h)
000Ah
EBTR0
WRT0
Bit 0
CP0
—
—
—