PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 298
PIC18F8520-I/PT
Manufacturer Part Number
PIC18F8520-I/PT
Description
80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F8520-IPT.pdf
(380 pages)
Specifications of PIC18F8520-I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
68
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
80-pin TQFP
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
40 MHz
Timers
2-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8520-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F8520-I/PT
Manufacturer:
MICRCOHI
Quantity:
20 000
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PIC18F6520/8520/6620/8620/6720/8720
SUBWFB
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
DS39609B-page 296
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ‘f’
Subtract W from f with Borrow
[ label ] SUBWFB
0
d
a
(f) – (W) – (C)
N, OV, C, DC, Z
Subtract W and the Carry flag
(borrow) from register ‘f’ (2’s com-
plement method). If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding the
BSR value. If ‘a’ is ‘1’, then the bank
will be selected as per the BSR
value (default).
1
1
SUBWFB
SUBWFB REG, 0, 0
SUBWFB
Read
0101
Q2
f
0x19
0x0D
1
0x0C
0x0D
1
0
0
0x1B
0x1A
0
0x1B
0x00
1
1
0
0x03
0x0E
1
0xF5
0x0E
0
0
1
[0,1]
[0,1]
255
10da
REG, 1, 0
REG, 1, 0
(0001 1001)
(0000 1101)
(0000 1011)
(0000 1101)
; result is positive
(0001 1011)
(0001 1010)
(0001 1011)
; result is zero
(0000 0011)
(0000 1101)
(1111 0100)
; [2’s comp]
(0000 1101)
; result is negative
Process
Data
Q3
dest
ffff
f [,d [,a]
destination
Write to
Q4
ffff
SWAPF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
=
=
register ‘f’
Swap f
[ label ] SWAPF f [,d [,a]
0
d
a
(f<3:0>)
(f<7:4>)
None
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is
‘1’, the result is placed in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ is ‘1’, then the
bank will be selected as per the
BSR value (default).
1
1
SWAPF
Read
0011
Q2
0x53
0x35
f
[0,1]
[0,1]
2004 Microchip Technology Inc.
255
REG, 1, 0
10da
dest<7:4>,
dest<3:0>
Process
Data
Q3
ffff
destination
Write to
Q4
ffff
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