PIC18F8520-I/PT Microchip Technology Inc., PIC18F8520-I/PT Datasheet - Page 71

• Manufacturer Part Number: PIC18F8520-I/PT
• Description: 80 PIN, 32 KB FLASH, 2048 RAM, 68 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F8520-I/PT

• A/d Inputs: 16-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 1024 Bytes
• Input Output: 68
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 80-pin TQFP
• Programmable Memory: 32K Bytes
• Ram Size: 2K Bytes
• Speed: 40 MHz
• Timers: 2-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

EXAMPLE 5-3:
5.5.2
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
5.5.3
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
TABLE 5-2:
 2004 Microchip Technology Inc.
TBLPTRU
TBPLTRH
TBLPTRL
TABLAT
INTCON
EECON2
EECON1
IPR2
PIR2
PIE2
Legend:
PROGRAM_MEMORY
Name
Required
Sequence
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
WRITE VERIFY
UNEXPECTED TERMINATION OF
WRITE OPERATION
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer High Byte (TBLPTR<7:0>)
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE
EEPROM Control Register 2 (not a physical register)
EEPGD
Bit 7
—
—
—
—
PIC18F6520/8520/6620/8620/6720/8720
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
BSF
BCF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
BSF
DECFSZ COUNTER_HI
BRA
BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
CFGS
CMIP
CMIE
CMIF
Bit 6
—
EECON1, EEPGD
EECON1, CFGS
EECON1, WREN
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
INTCON, GIE
PROGRAM_LOOP
EECON1, WREN
bit 21
Bit 5
—
—
—
—
Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)
FREE
Bit 4
INTE
EEIP
EEIF
EEIE
WRERR
BCLIP
BCLIF
BCLIE
RBIE
Bit 3
; point to Flash program memory
; access Flash program memory
; enable write to memory
; disable interrupts
; write 55H
; write AAH
; start program (CPU stall)
; re-enable interrupts
; loop until done
; disable write to memory
TMR0IF
WREN
LVDIP
LVDIF
LVDIE
5.5.4
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 23.0 “Special Features of the
CPU” for more detail.
5.6
See Section 23.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
Bit 2
TMR3IP
TMR3IF
TMR3IE
Flash Program Operation During
Code Protection
INTF
Bit 1
WR
PROTECTION AGAINST
SPURIOUS WRITES
CCP2IP
CCP2IF
CCP2IE
RBIF
Bit 0
RD
--00 0000
0000 0000
0000 0000
0000 0000
0000 0000
xx-0 x000
---1 1111
---0 0000
---0 0000
POR, BOR
Value on
—
DS39609B-page 69
--00 0000
0000 0000
0000 0000
0000 0000
0000 0000
uu-0 u000
---1 1111
---0 0000
---0 0000
Value on
all other
Resets
—