PIC18F1320-I/SO Microchip Technology Inc., PIC18F1320-I/SO Datasheet
PIC18F1320-I/SO
Specifications of PIC18F1320-I/SO
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PIC18F1320-I/SO Summary of contents
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... Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology 2004 Microchip Technology Inc. PIC18F1220/1320 18/20/28-Pin High-Performance, Data Sheet DS39605C ...
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... October 2003. The Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2004 Microchip Technology Inc. L ® code hopping OQ ...
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... Allows for safe shutdown if peripheral clock stops Program Memory Device Flash # Single-Word (bytes) Instructions PIC18F1220 4K 2048 PIC18F1320 8K 4096 2004 Microchip Technology Inc. PIC18F1220/1320 Peripheral Highlights: • High current sink/source 25 mA/25 mA • Three external interrupts • Enhanced Capture/Compare/PWM (ECCP) module: - One, two or four PWM outputs ...
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... RA2/AN2/V - REF RB6/PGC/T1OSO/ T13CKI/P1C/KBI2 RA3/AN3/V + REF RB5/PGM/KBI1 RB4/AN6/RX/ RB0/AN4/INT0 DT/KBI0 RB1/AN5/TX/ CK/INT1 21 1 OSC1/CLKI/RA7 2 20 OSC2/CLKO/RA6 PIC18F1X20 RB7/PGD/T1OSI/P1D/KBI3 7 15 RB6/PGC/T1OSO/T13CKI/P1C/KBI2 1 20 RB3/CCP1/P1A 2 19 RB2/P1B/INT2 3 18 OSC1/CLKI/RA7 4 17 OSC2/CLKO/RA6 RB7/PGD/T1OSI P1D/KBI3 RB6/PGC/T1OSO T13CKI/P1C/KBI2 RB5/PGM/KBI1 9 12 RB4/AN6/RX DT/KBI0 2004 Microchip Technology Inc. ...
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... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 295 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 295 Index .................................................................................................................................................................................................. 297 On-Line Support................................................................................................................................................................................. 305 Systems Information and Upgrade Hot Line ...................................................................................................................................... 305 Reader Response .............................................................................................................................................................................. 306 PIC18F1220/1320 Product Identification System .............................................................................................................................. 307 2004 Microchip Technology Inc. PIC18F1220/1320 DS39605C-page 3 ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS39605C-page 4 2004 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F1220 • PIC18F1320 This family offers the advantages of all PIC18 microcon- trollers – namely, high computational performance at an economical price – with the addition of high endurance Enhanced Flash program memory. On top of these fea- ...
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... Figure 1-1. The devices are differentiated from each other only in the amount of on-chip Flash program memory (4 Kbytes for the PIC18F1220 device, 8 Kbytes for the PIC18F1320 device). These and other features are summarized in Table 1-1. TABLE 1-1: DEVICE FEATURES ...
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... FIGURE 1-1: PIC18F1220/1320 BLOCK DIAGRAM Table Pointer <2> 21 inc/dec logic 21 21 PCLATU 20 Address Latch Program Memory (4 Kbytes) PIC18F1220 (8 Kbytes) PIC18F1320 Data Latch 16 Table Latch 8 ROM Latch Instruction Register Instruction Decode & Control (2) OSC1 Power-up Timing (2) OSC2 Generation Oscillator Start-up Timer INTRC ...
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... A/D reference voltage (high) input. 28 I/O ST/OD Digital I/O. Open-drain when configured as output Timer0 external clock input. See the MCLR/V See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. CMOS = CMOS compatible input or output I = Input P = Power ) DD Description /RA5 pin. PP 2004 Microchip Technology Inc. ...
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... Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-drain (no P diode to V 2004 Microchip Technology Inc. PIC18F1220/1320 Pin Buffer Type Type QFN PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... PIC18F1220/1320 NOTES: DS39605C-page 10 2004 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F1220 and PIC18F1320 devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. HSPLL ...
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... FIGURE 2-3: HS Oscillator Enable (from Configuration Register 1H when DD OSC2 Crystal OSC1 Osc of external EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) Open OSC2 PLL BLOCK DIAGRAM PLL Enable Phase F IN Comparator F OUT Loop Filter 4 VCO SYSCLK 2004 Microchip Technology Inc. ...
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... CONFIGURATION) OSC1/CLKI Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) 2004 Microchip Technology Inc. PIC18F1220/1320 2.5 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply ...
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... Code execution continues during this shift. There is no indication that the shift has occurred. Operation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency. /4, OSC 8 clock cycles (approximately 2004 Microchip Technology Inc. ...
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... The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power managed mode. 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R/W-0 R/W-0 R/W-0 — ...
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... MHz 101 1 MHz 100 500 kHz 8 MHz 011 (INTOSC) 250 kHz 010 125 kHz 001 31 kHz 000 Start-ups. The T1RUN secondary clock source when Clock OSCCON<1:0> Control Peripherals T1OSC Internal Oscillator CPU IDLEN WDT, FSCM 2004 Microchip Technology Inc. bit ...
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... SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block (RC modes Timer1 oscillator (Secondary modes Primary oscillator (Sleep and PRI_IDLE modes) Note 1: Depends on state of the IESO bit in Configuration Register 1H. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 (1) R/W-0 R/W-0 R R-0 IRCF1 ...
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... EC INTIO modes are used as the primary clock source. OSC1 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level OSC2 Pin 2004 Microchip Technology Inc. ...
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... RC_IDLE 1 1x Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2004 Microchip Technology Inc. PIC18F1220/1320 For PIC18F1220/1320 devices, the power managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when trig- gered by an interrupt, a Reset or a WDT time-out (PRI_RUN mode is the normal full power execution mode ...
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... SCS bits are unchanged during and after the wake-up. Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode). 2004 Microchip Technology Inc ...
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... SLEEP instruction. This is both the Reset state of the OSCCON register and the setting that selects Sleep mode. This maintains compatibility with other PICmicro devices that do not offer power managed modes. 2004 Microchip Technology Inc. PIC18F1220/1320 WDT Time-out Peripherals are causes a ... ...
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... TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) OSC1 (1) T OST PLL Clock Output CPU Clock Peripheral Clock Program PC Counter Wake Event Note 1024 (approx). These intervals are not shown to scale. OST OSC PLL DS39605C-page PLL ( OSTS bit Set 2004 Microchip Technology Inc. ...
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... Peripheral Clock Program PC Counter Wake Event 2004 Microchip Technology Inc. PIC18F1220/1320 When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately required between the wake event and code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wake- up, the OSTS bit remains set ...
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... T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The Timer1 oscillator continues to run Clock Transition PLL ( Clock Transition OSTS bit Set 2004 Microchip Technology Inc. ...
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... These intervals are not shown to scale. OST OSC PLL 2004 Microchip Technology Inc. PIC18F1220/1320 instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
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... Figure 3-6). When the clock switch is complete, the Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set and the pri- mary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up Clock Transition 2004 Microchip Technology Inc. ...
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... INTRC OSC1 CPU Clock Peripheral Clock Program PC Counter 2004 Microchip Technology Inc. PIC18F1220/1320 Note: Caution should be used when modifying a single IRCF bit possible to select a higher clock speed than is supported by the low V Improper device operation may result if the V If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
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... On all exits from Low-Power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”). 2004 Microchip Technology Inc. ...
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... Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”). 2004 Microchip Technology Inc. PIC18F1220/1320 Power Activity during Wake-up from ...
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... RC_IDLE modes when the INTRC clock source is selected. Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made and in some cases, how large a change is needed. Three examples follow but other techniques may be used. 2004 Microchip Technology Inc. or temperature ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. 2004 Microchip Technology Inc. PIC18F1220/1320 3.6.3 EXAMPLE – CCP IN CAPTURE ...
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... PIC18F1220/1320 NOTES: DS39605C-page 32 2004 Microchip Technology Inc. ...
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... INTRC 11-bit Ripple Counter Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 4-1 for time-out situations. 2004 Microchip Technology Inc. PIC18F1220/1320 Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... DD for less than T . The chip will BOR rises above V DD BOR ; it then will keep the chip in BOR additional time delay, T PWRT drops below V while the DD BOR rises above V , the Power-up Timer BOR 2004 Microchip Technology Inc. . ...
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... Legend unchanged unknown, – = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2004 Microchip Technology Inc. PIC18F1220/1320 (2) Power-up and Brown-out ...
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... N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu 2004 Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 5 of PORTA is enabled if MCLR is disabled. 2004 Microchip Technology Inc. PIC18F1220/1320 MCLR Resets Power-on Reset, ...
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... Microchip Technology Inc. ...
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... V DD MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2004 Microchip Technology Inc. PIC18F1220/1320 DD T PWRT T OST T PWRT T OST T PWRT T OST , V RISE < T ...
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... TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL DS39605C-page > ISE PWRT T OST T PWRT T OST T PLL ) PWRT ) DD 2004 Microchip Technology Inc. ...
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... The PIC18F1220 has 4 Kbytes of Flash memory and can store up to 2,048 single-word instructions. The PIC18F1320 has 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. ...
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... This is not the same as a Reset, as the contents of the SFRs are not affected. Return Address Stack 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 STKPTR<4:0> 00010 2004 Microchip Technology Inc. ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R/W-0 R/W-0 R/W-0 — ...
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... The PC increments address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instruc- tions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. 2004 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2004 Microchip Technology Inc. PIC18F1220/1320 5.6 Instruction Flow/Pipelining An “ ...
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... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 2004 Microchip Technology Inc. ...
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... Data is transferred to/from program memory, one byte at a time. The table read/table write operation is discussed further in Section 6.1 “Table Reads and Table Writes”. 2004 Microchip Technology Inc. PIC18F1220/1320 5.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory ...
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... The BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the Bank used by the instruction. 2004 Microchip Technology Inc. ...
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... Note 1: Unimplemented registers are read as ‘0’. 2: This is not a physical register. 2004 Microchip Technology Inc. PIC18F1220/1320 The SFRs can be classified into two sets: those asso- ciated with the “core” function and those related to the peripheral functions. Those registers related to the “ ...
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... DC C 37, 55 ---x xxxx 37, 101 0000 0000 37, 101 xxxx xxxx T0PS1 T0PS0 37, 99 1111 1111 SCS1 SCS0 37, 17 0000 q000 LVDL1 LVDL0 37, 167 --00 0101 — SWDTEN 37, 180 --- ---0 POR BOR 35, 56, 84 0--1 11q0 2004 Microchip Technology Inc. ...
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... Bit 21 of the PC is only available in Test mode and Serial Programming modes. 4: The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only. 2004 Microchip Technology Inc. PIC18F1220/1320 Bit 4 Bit 3 ...
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... Registers” provides a description of indirect address- ing, which allows linear addressing of the entire RAM space. Direct Addressing (3) 7 From Opcode 0 (3) 00h 01h 000h 100h Data (1) Memory 0FFh 1FFh Bank 0 Bank 1 0Eh 0Fh E00h F00h EFFh FFFh Bank 14 Bank 15 2004 Microchip Technology Inc. ...
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... FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. 2004 Microchip Technology Inc. PIC18F1220/1320 If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all ‘0’s are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected ...
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... FIGURE 5-9: INDIRECT ADDRESSING Indirect Addressing 3 11 Location Select Note 1: For register file map detail, see Table 5-1. DS39605C-page 54 0h RAM Address FFFh 12 File Address = Access of an Indirect Addressing Register File FSR FSRnH:FSRnL 0000h Data (1) Memory 0FFFh 2004 Microchip Technology Inc. ...
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... Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the Status reg- ister, because these instructions do not affect the bits in the Status register ...
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... Power-on Resets may be detected. U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2004 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2004 Microchip Technology Inc. PIC18F1220/1320 The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
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... Program memory is read using table read instructions. See Section 6.3 “Reading the Flash Program Memory” regarding table reads. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software. 2004 Microchip Technology Inc. TABLAT ...
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... Initiates a memory read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Read completed Legend Readable bit W = Writable bit x = Bit is unknown 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R/W-0 R/W-x R/W-0 — FREE ...
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... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 LONG WRITE – TBLPTR<21:3> READ or WRITE – TBLPTR<21:0> TBLPTRL 0 2004 Microchip Technology Inc. ...
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... TBLRD*+ MOVFW TABLAT MOVWF WORD_ODD 2004 Microchip Technology Inc. PIC18F1220/1320 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
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... Execute a NOP. 9. Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; point to FLASH program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts 2004 Microchip Technology Inc. ...
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... EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN bit to enable byte writes. 2004 Microchip Technology Inc. PIC18F1220/1320 Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction must be executed 8 times for each programming operation ...
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... FLASH program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; Required sequence ; write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts ; number of write buffer groups of 8 bytes ; point to buffer ; number of bytes in holding register 2004 Microchip Technology Inc. ...
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... Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2004 Microchip Technology Inc. PIC18F1220/1320 ; get low byte of buffer data and increment FSR0 ; present data to table latch ; short write ; to internal TBLWT holding register, increment TBLPTR ...
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... PIC18F1220/1320 NOTES: DS39605C-page 66 2004 Microchip Technology Inc. ...
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... Control bit, EEPGD, determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. 2004 Microchip Technology Inc. PIC18F1220/1320 Control bit, CFGS, determines if the access will be to the configuration registers or to program memory/data EEPROM memory ...
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... Legend Readable bit W = Writable bit x = Bit is unknown DS39605C-page 68 U-0 R/W-0 R/W-x R/W-0 — FREE WRERR WREN S = Settable only U = Unimplemented bit, read as ‘0’ Value at POR ‘1’ = Bit is set R/S-0 R/S bit 0 ‘0’ = Bit is cleared 2004 Microchip Technology Inc. ...
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... BSF INTCON, GIE SLEEP BCF EECON1, WREN 2004 Microchip Technology Inc. PIC18F1220/1320 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
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... POR, BOR Resets RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 — — RD xx-0 x000 uu-0 u000 — 1--1 -11- 1--1 -11- — 0--0 -00- 0--0 -00- — 0--0 -00- 0--0 -00- 2004 Microchip Technology Inc. ...
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... MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL 2004 Microchip Technology Inc. PIC18F1220/1320 Making the multiplier execute in a single cycle gives the following advantages: • Higher computational throughput • Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors ...
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... WREG ; ADDWFC RES3 BTFSS ARG2H ARG2H:ARG2L neg? BRA SIGN_ARG1 ; no, check ARG1 MOVF ARG1L SUBWF RES2 ; MOVF ARG1H SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H ARG1H:ARG1L neg? BRA CONT_CODE ; no, done MOVF ARG2L SUBWF RES2 ; MOVF ARG2H SUBWFB RES3 ; CONT_CODE : 2004 Microchip Technology Inc ...
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... Individual interrupts can be disabled through their corresponding enable bits. 2004 Microchip Technology Inc. PIC18F1220/1320 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON< ...
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... INT2IE INT2IP IPEN IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP 2004 Microchip Technology Inc. Wake- Low-Power Mode Interrupt to CPU Vector to Location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEL\PEIE GIE\GIEH ...
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... A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
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... This feature allows for software polling. DS39605C-page 76 R/W-1 R/W-1 U-0 R/W-1 INTEDG1 INTEDG2 — TMR0IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown 2004 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R/W-0 ...
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... R-0 R-0 U-0 R/W-0 RCIF TXIF — CCP1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared 2004 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
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... TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software TMR3 register did not overflow bit 0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 U-0 R/W-0 U-0 — — EEIF — ...
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... Legend Readable bit -n = Value at POR DS39605C-page 80 R/W-0 R/W-0 U-0 R/W-0 RCIE TXIE — CCP1IE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown 2004 Microchip Technology Inc. ...
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... Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 U-0 R/W-0 U-0 — — EEIE — Writable bit U = Unimplemented bit, read as ‘0’ ...
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... Legend Readable bit -n = Value at POR DS39605C-page 82 R/W-1 R/W-1 U-0 R/W-1 RCIP TXIP — CCP1IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown 2004 Microchip Technology Inc. ...
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... High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 Unimplemented: Read as ‘0’ Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 U-0 R/W-1 U-0 — — EEIP — Writable bit U = Unimplemented bit, read as ‘ ...
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... For details of bit operation, see Register 5-3. Legend Readable bit -n = Value at POR DS39605C-page 84 U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown 2004 Microchip Technology Inc. ...
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... USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2004 Microchip Technology Inc. PIC18F1220/1320 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow (FFh 00h) in the TMR0 register will set flag bit, TMR0IF. In 16-bit mode, an overflow (FFFFh in the TMR0H:TMR0L registers will set flag bit, TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON< ...
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... PIC18F1220/1320 NOTES: DS39605C-page 86 2004 Microchip Technology Inc. ...
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... Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. 2004 Microchip Technology Inc. PIC18F1220/1320 The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA ...
Page 90
... I/O pins have protection diodes to V BLOCK DIAGRAM OF RA4/T0CKI PIN I/O pin N Data Latch Schmitt CK Q Trigger TRIS Latch Input Buffer and BLOCK DIAGRAM OF OSC1/CLKI/RA7 PIN To Oscillator Data Latch N I/O pin Schmitt Trigger Input Buffer and 2004 Microchip Technology Inc. (1) (1) ...
Page 91
... Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: RA5 is an input only if MCLR is disabled. 2004 Microchip Technology Inc. PIC18F1220/1320 Schmitt Trigger Latch Q ...
Page 92
... RD LATB PORTB Schmitt Trigger Buffer INTx To A/D Converter Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2004 Microchip Technology Inc Weak P Pull-up I/O (1) pin TTL Input Buffer D EN and V ...
Page 93
... RBPU Analog Input Mode Data Bus WR LATB or PORTB WR TRISB RD PORTB Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2004 Microchip Technology Inc. PIC18F1220/1320 1 0 Data Latch TRIS Latch ...
Page 94
... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). DS39605C-page 92 (2) RBPU 1 0 Data Latch TRIS Latch TRISB RD LATB Q Schmitt Trigger and Weak P Pull-up (1) RB2 pin TTL Input Buffer PORTB 2004 Microchip Technology Inc. ...
Page 95
... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: ECCP1 pin output enable active for any PWM mode and Compare mode, where CCP1M<3:0> = 1000 or 1001. 4: ECCP1 pin input enable active for Capture mode only. 2004 Microchip Technology Inc. PIC18F1220/1320 ...
Page 96
... I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). DS39605C-page (2) RBPU P Weak Pull- PORTB EN Q3 Schmitt Trigger RX/DT Input Analog Input Mode and RB4 pin TTL Input Buffer Q1 2004 Microchip Technology Inc. ...
Page 97
... From other RB7:RB5 and RB4 pins RB7:RB5 in Serial Programming Mode Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2004 Microchip Technology Inc. PIC18F1220/1320 V DD Weak P Pull-up Data Latch D ...
Page 98
... I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). DS39605C-page Weak Pull- TTL Schmitt Buffer Trigger PORTB EN Q3 and RB6 pin Timer1 Oscillator From RB7 pin 2004 Microchip Technology Inc. ...
Page 99
... TRIS Latch RD TRISB T1OSCEN RD PORTB Set RBIF From other RB7:RB4 pins PGD Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2004 Microchip Technology Inc. PIC18F1220/1320 V DD Weak P Pull- ...
Page 100
... POR, BOR Resets RB0 xxxq qqqq uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RBIF 0000 000x 0000 000u RBIP 1111 -1-1 1111 -1-1 INT1IF 11-0 0-00 11-0 0-00 PCFG0 -000 0000 -000 0000 2004 Microchip Technology Inc. ...
Page 101
... Prescale value 000 = 1:2 Prescale value Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 102
... T0PS2, T0PS1, T0PS0 1 Sync with Internal TMR0L Clocks Delay PSA Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> 2004 Microchip Technology Inc. ...
Page 103
... RA7 RA6 Legend unknown unchanged, – = unimplemented locations read as Note 1: RA6 and RA7 are enabled as I/O pins, depending on the oscillator mode selected in Configuration Word 1H. 2004 Microchip Technology Inc. PIC18F1220/1320 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution) ...
Page 104
... PIC18F1220/1320 NOTES: DS39605C-page 102 2004 Microchip Technology Inc. ...
Page 105
... Enables Timer1 0 = Stops Timer1 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 106
... TMR1CS 8 CCP Special Event Trigger TMR1 CLR TMR1L TMR1ON on/off 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Synchronized 0 Clock Input 1 Synchronize det 2 Peripheral Clocks Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 Peripheral Clocks 2004 Microchip Technology Inc. ...
Page 107
... If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead), or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation. 2004 Microchip Technology Inc. PIC18F1220/1320 FIGURE 12-3: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR ...
Page 108
... The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. a “special event trigger” 2004 Microchip Technology Inc. ...
Page 109
... RETURN MOVLW .01 MOVWF hours RETURN 2004 Microchip Technology Inc. PIC18F1220/1320 Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals necessary to pre- load it; the simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered ...
Page 110
... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000u TMR1IF -000 -000 -000 -000 TMR1IE -000 -000 -000 -000 TMR1IP -111 -111 -111 -111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2004 Microchip Technology Inc. ...
Page 111
... Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...
Page 112
... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000u TMR1IF -000 -000 -000 -000 TMR1IE -000 -000 -000 -000 TMR1IP -111 -111 -111 -111 0000 0000 0000 0000 1111 1111 1111 1111 2004 Microchip Technology Inc. ...
Page 113
... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 Figure 14 simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. ...
Page 114
... Oscillator Clock TMR3CS T3CKPS1:T3CKPS0 8 CCP Special Event Trigger T3CCPx TMR3 CLR TMR3L TMR3ON On/Off OSC Internal 0 (1) Clock TMR3CS Synchronized Clock Input Synchronize det 2 Peripheral Clocks Synchronized 0 Clock Input 1 T3SYNC Synchronize Prescaler det 2 Peripheral Clocks T3CKPS1:T3CKPS0 2004 Microchip Technology Inc. ...
Page 115
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T3CON RD16 — T3CKPS1 T3CKPS0 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. 2004 Microchip Technology Inc. PIC18F1220/1320 14.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to ...
Page 116
... PIC18F1220/1320 NOTES: DS39605C-page 114 2004 Microchip Technology Inc. ...
Page 117
... PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 The control register for CCP1 is shown in Register 15-1. In addition to the expanded functions of the CCP1CON register, the ECCP module has two additional ...
Page 118
... The user should keep bit, CCP1IE (PIE1<2>), clear while changing capture modes to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode. and <3:0>, RB7 RB7/PGD/T1OSI/KBI3 RB7/PGD/T1OSI/KBI3 P1D 2004 Microchip Technology Inc. ...
Page 119
... Clearing the CCP1CON register will force the RB3/CCP1/P1A compare output latch to the default low level. This is not the PORTB I/O data latch. 2004 Microchip Technology Inc. PIC18F1220/1320 recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “ ...
Page 120
... CCP1M0 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ADON 00-0 0000 00-0 0000 2004 Microchip Technology Inc. ...
Page 121
... PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) 2004 Microchip Technology Inc. PIC18F1220/1320 15.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON< ...
Page 122
... P1A Inactive P1B Modulated (Full-Bridge, 11 Reverse) P1C Active P1D Inactive DS39605C-page 120 P1M1<1:0> CCP1M<3:0> CCP1/P1A TRISB<3> P1B TRISB<2> Output Q Controller P1C TRISB<6> P1D TRISB<7> CCP1DEL 0 Duty Cycle Period (1) (1) Delay Delay RB3/CCP1/P1A RB2/P1B/INT2 RB6/PGC/T1OSO/T13CKI/ P1C/KBI2 RB7/PGD/T1OSI/P1D/KBI3 PR2+1 2004 Microchip Technology Inc. ...
Page 123
... OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 15.5.6 “Programmable Dead-Band Delay”). 2004 Microchip Technology Inc. PIC18F1220/1320 0 Duty Cycle Period (1) (1) Delay Delay PR2+1 ...
Page 124
... P1B ( Dead-Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. FET Driver P1A Load FET Driver P1B V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT (ACTIVE-HIGH) Period td (1) ( FET Driver FET Driver 2004 Microchip Technology Inc. ...
Page 125
... P1A P1B P1C P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2004 Microchip Technology Inc. PIC18F1220/1320 The TRISB<3:2> and TRISB<7:6> bits must be cleared to make the P1A, P1B, P1C and P1D pins output. Period Duty Cycle Period ...
Page 126
... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD 2004 Microchip Technology Inc. ...
Page 127
... External Switch C External Switch D Potential Shoot-Through Current Note the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF 2004 Microchip Technology Inc. PIC18F1220/1320 (1) PWM Period DC One Timer2 Count Forward Period t1 DC PWM Period (2) ...
Page 128
... PDC4 PDC3 / cycles between the scheduled time when a PWM signal should OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PDC2 PDC1 PDC0 bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 129
... PSSBDn: Pins B and D Shutdown State Control bits 00 = Drive Pins B and D to ‘0’ Drive Pins B and D to ‘1’ Pins B and D tri-state Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 R/W-0 R/W-0 R/W-0 R/W-0 PSSAC1 PSSAC0 W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 130
... PWM cycle is indicated by the TMR2IF bit being set as the second PWM period begins. PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle PWM Period PWM Period Dead Time Dead Time Duty Cycle Duty Cycle ECCPASE Cleared by Firmware 2004 Microchip Technology Inc. ...
Page 131
... Wait until TMR2 overflows (TMR2IF bit is set). • Enable the CCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRISB bits. • Clear the ECCPASE bit (ECCPAS<7>). 2004 Microchip Technology Inc. PIC18F1220/1320 15.5.10 OPERATION IN LOW-POWER MODES In the Low-Power Sleep mode, all clock sources are disabled ...
Page 132
... CCP1M0 0000 0000 0000 0000 PSSBD0 0000 0000 0000 0000 PDC0 0000 0000 uuuu uuuu SCS0 0000 qq00 0000 qq00 2004 Microchip Technology Inc. ...
Page 133
... Baud Rate Control (BAUDCTL) These are detailed in on the following pages in Register 16-1, Register 16-2 and respectively. 2004 Microchip Technology Inc. PIC18F1220/1320 16.1 Asynchronous Operation in Power Managed Modes The EUSART may operate in Asynchronous mode while the peripheral clocks are being provided by the internal oscillator block ...
Page 134
... R = Readable bit -n = Value at POR DS39605C-page 132 R/W-0 R/W-0 U-0 TX9 TXEN SYNC SENDB W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 135
... Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ...
Page 136
... R = Readable bit -n = Value at POR DS39605C-page 134 R-1 U-0 R/W-0 R/W-0 — SCKP BRG16 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared U-0 R/W-0 R/W-0 — WUE ABDEN bit Bit is unknown 2004 Microchip Technology Inc. ...
Page 137
... Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.16% 2004 Microchip Technology Inc. PIC18F1220/1320 16.2.1 POWER MANAGED MODE OPERATION The system clock is used to generate the desired baud rate; however, when a power managed mode is entered, the clock source may be operating at a differ- ent frequency than in PRI_RUN mode ...
Page 138
... SPBRG Actual SPBRG % % value Rate value Error (K) (decimal) (decimal) — — — — 129 1201 -0.16 103 64 2403 -0. 9615 -0. — — — 2 — — — 1 — — — SPBRG % value (decimal — — — — — 2004 Microchip Technology Inc. ...
Page 139
... Microchip Technology Inc. PIC18F1220/1320 SYNC = 0, BRGH = 1, BRG16 = 20.000 MHz F = 10.000 MHz OSC OSC SPBRG Actual % Rate value Rate Error Error (K) (K) (decimal) — ...
Page 140
... SPBRG % value (decimal) 832 207 103 25 12 — — — — 2004 Microchip Technology Inc. ...
Page 141
... Idle. The RCIF interrupt is set once the fifth rising edge detected. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. 2004 Microchip Technology Inc. PIC18F1220/1320 Note the user to determine that the incoming character baud rate is within the range of the selected BRG clock source ...
Page 142
... Note 1: The TSR register is not mapped in data memory not available to the user. 2: Flag bit, TXIF, is set when enable bit, TXEN, is set. 001Ch Edge #5 Edge #4 Bit 5 Bit 7 Bit 6 Stop Bit Auto-Cleared 1Ch 00h ), the TXREG register is CY 2004 Microchip Technology Inc. ...
Page 143
... CY Reg. Empty Flag) Word 1 TRMT bit Transmit Shift Reg (Transmit Shift Reg. Empty Flag) 2004 Microchip Technology Inc. PIC18F1220/1320 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. ...
Page 144
... RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 -1-1 0-00 -1-1 0-00 0000 0000 0000 0000 0000 0000 0000 0000 2004 Microchip Technology Inc. ...
Page 145
... Baud Rate CLK BRG16 SPBRGH SPBRG Baud Rate Generator RB4/AN6/RX/DT/KBI0 Pin Buffer and Control SPEN 2004 Microchip Technology Inc. PIC18F1220/1320 16.3.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. ...
Page 146
... RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 ABDEN -1-1 0-00 -1-1 0-00 0000 0000 0000 0000 0000 0000 0000 0000 2004 Microchip Technology Inc. ...
Page 147
... If the wake-up event requires a long oscillator warm-up time, the WUE bit may be cleared while the primary clock is still starting. 2: The EUSART remains in Idle while the WUE bit is set. 2004 Microchip Technology Inc. PIC18F1220/1320 and cause data or framing errors. To work properly, therefore, the initial character in the transmission must be all ‘ ...
Page 148
... FIFO buffer. 5. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. 2004 Microchip Technology Inc. ...
Page 149
... Write to TXREG Dummy Write BRG Output (Shift Clock) TX (pin) Start Bit TXIF bit TRMT bit SENDB 2004 Microchip Technology Inc. PIC18F1220/1320 7. Enable Auto-Baud Rate Detect. Set ABDEN. 8. Return from the interrupt. Allow the primary clock to start and stabilize (PRI_RUN or PRI_IDLE). 9. ...
Page 150
... Start transmission by loading data to the TXREG register using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set Q1Q2 bit 1 bit 2 bit 7 bit 0 Word 1 ), the TXREG is empty CYCLE bit 1 bit 7 Word 2 ‘1’ 2004 Microchip Technology Inc. ...
Page 151
... SPBRGH Baud Rate Generator Register High Byte SPBRG Baud Rate Generator Register Low Byte Legend unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission. 2004 Microchip Technology Inc. PIC18F1220/1320 bit 0 bit 2 bit 1 Bit 4 ...
Page 152
... RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set bit 1 bit 2 bit 3 bit 4 bit bit 6 bit 7 ‘0’ 2004 Microchip Technology Inc. ...
Page 153
... SPBRGH Baud Rate Generator Register High Byte SPBRG Baud Rate Generator Register Low Byte Legend unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception. 2004 Microchip Technology Inc. PIC18F1220/1320 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE ...
Page 154
... TMR1IP -111 -111 -111 -111 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 ABDEN -1-1 0-00 -1-1 0-00 0000 0000 0000 0000 0000 0000 0000 0000 2004 Microchip Technology Inc. ...
Page 155
... SPBRG Baud Rate Generator Register Low Byte – Legend unknown, = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception. 2004 Microchip Technology Inc. PIC18F1220/1320 To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC ...
Page 156
... PIC18F1220/1320 NOTES: DS39605C-page 154 2004 Microchip Technology Inc. ...
Page 157
... A/D converter module is disabled Note 1: Performing a conversion on unimplemented channels returns full-scale results. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 The module has five registers: • A/D Result High Register (ADRESH) • A/D Result Low Register (ADRESL) • A/D Control Register 0 (ADCON0) • ...
Page 158
... R = Readable bit -n = Value at POR DS39605C-page 156 R/W-0 R/W-0 R/W-0 R/W-0 PCFG5 PCFG4 PCFG3 PCFG2 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared 2004 Microchip Technology Inc. R/W-0 R/W-0 PCFG1 PCFG0 bit Bit is unknown ...
Page 159
... A/D RC oscillator) RC Note: If the A/D F added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R/W-0 R/W-0 R/W-0 — ACQT2 ACQT1 ...
Page 160
... A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 17-1. CHS2:CHS0 V AIN (Input Voltage) VCFG1:VCFG0 REFH x1 1x REFL and 111 110 (1) AN6 101 AN5 100 AN4 011 AN3/V + REF 010 AN2/V - REF 001 AN1 000 AN0 2004 Microchip Technology Inc. ...
Page 161
... SS = sampling switch C = sample/hold capacitance (from DAC) HOLD R = sampling switch resistance SS 2004 Microchip Technology Inc. PIC18F1220/1320 A/D Conversion: 1. Configure the A/D module: • Configure analog pins, voltage reference and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D acquisition time (ADCON2) • ...
Page 162
... HOLD COFF . This calculation is ACQ the following application system = 120 pF = 2.5 k 1/2 LSb = (system max time = 0 + and V - References REF REF and AV sources, the source imped and V - voltage sources must be REF + and V - external REF REF 2004 Microchip Technology Inc. ...
Page 163
... For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. 4: Low-power devices only. 2004 Microchip Technology Inc. PIC18F1220/1320 17.4 Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as T ...
Page 164
... Analog levels on a digitally configured input will converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device’s specification limits. 2004 Microchip Technology Inc. be accurately ...
Page 165
... Time (Holding capacitor is disconnected) Set GO bit (Holding capacitor continues acquiring input) 2004 Microchip Technology Inc. PIC18F1220/1320 Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D ...
Page 166
... ADON 00-0 0000 00-0 0000 PCFG0 -000 0000 -000 0000 ADCS0 0-00 0000 0-00 0000 RA0 qq0x 0000 uu0u 0000 qq-1 1111 11-1 1111 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 xxxx xxxx uuuu uuuu 2004 Microchip Technology Inc. ...
Page 167
... TYPICAL LOW-VOLTAGE DETECT APPLICATION Time 2004 Microchip Technology Inc. PIC18F1220/1320 Figure 18-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage V the LVD logic generates an interrupt. This occurs at time T ...
Page 168
... Internally Generated Reference Voltage 1.2V LVDIN (Figure 18-3). This gives users flexibility, because it allows them to configure the Low-Voltage Detect interrupt to occur at any voltage in the valid operating range VxEN BODEN EN BGAP LVDIF LVD Control Register LVDEN LVD 2004 Microchip Technology Inc. ...
Page 169
... Reserved 0000 = Reserved Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage of the device, are not tested. Legend Readable bit -n = Value at POR 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 R-0 R/W-0 R/W-0 — IRVST LVDEN ...
Page 170
... Figure 18-4 shows typical waveforms that the LVD module may be used to detect. LVDIF may not be set. T IVRST LVDIF cleared in software T IVRST LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists 2004 Microchip Technology Inc. V LVD V LVD ...
Page 171
... The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter D022B. 2004 Microchip Technology Inc. PIC18F1220/1320 18.3 Operation During Sleep When enabled, the LVD circuitry continues to operate during Sleep ...
Page 172
... PIC18F1220/1320 NOTES: DS39605C-page 170 2004 Microchip Technology Inc. ...
Page 173
... Shaded cells are unimplemented, read as ‘0’. Note 1: See Register 19-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. 2004 Microchip Technology Inc. PIC18F1220/1320 The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up ...
Page 174
... XT oscillator 0000 = LP oscillator Legend Readable bit -n = Value when device is unprogrammed DS39605C-page 172 U-0 U-0 R/P-1 R/P-1 — — FOSC3 FOSC2 P = Programmable bit U = Unimplemented bit, read as ‘0’ Unchanged from programmed state R/P-1 R/P-1 FOSC1 FOSC0 bit 0 2004 Microchip Technology Inc. ...
Page 175
... PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Note 1: The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled. Legend Readable bit -n = Value when device is unprogrammed 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 U-0 R/P-1 — — — ...
Page 176
... WDT disabled (control is placed on the SWDTEN bit) Legend Readable bit -n = Value when device is unprogrammed DS39605C-page 174 U-0 U-0 R/P-1 R/P-1 — — WDTPS3 WDTPS2 P = Programmable bit U = Unimplemented bit, read as ‘0’ Unchanged from programmed state R/P-1 R/P-1 R/P-1 WDTPS1 WDTPS0 WDTEN bit 0 2004 Microchip Technology Inc. ...
Page 177
... Timer1 crystal may be damaged. If ICSP or ICD operations are required, the crystal should be disconnected from the circuit (disconnect either lead) or installed after programming. The oscillator loading capacitors may remain in-circuit during ICSP or ICD operation. 2004 Microchip Technology Inc. PIC18F1220/1320 U-0 U-0 ...
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... Unimplemented: Read as ‘0’ bit 1 CP1: Code Protection bit (PIC18F1320 Block 1 (001000-001FFFh) not code-protected 0 = Block 1 (001000-001FFFh) code-protected bit 0 CP0: Code Protection bit (PIC18F1320 Block 0 (00200-000FFFh) not code-protected 0 = Block 0 (00200-000FFFh) code-protected bit 1 CP1: Code Protection bit (PIC18F1220 Block 1 (000800-000FFFh) not code-protected 0 = Block 1 (000800-000FFFh) code-protected ...
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... Unimplemented: Read as ‘0’ bit 1 WRT1: Write Protection bit (PIC18F1320 Block 1 (001000-001FFFh) not write-protected 0 = Block 1 (001000-001FFFh) write-protected bit 0 WRT0: Write Protection bit (PIC18F1320 Block 0 (00200-000FFFh) not write-protected 0 = Block 0 (00200-000FFFh) write-protected bit 1 WRT1: Write Protection bit (PIC18F1220 Block 1 (000800-000FFFh) not write-protected 0 = Block 1 (000800-000FFFh) write-protected ...
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... Block 1 (001000-001FFFh) not protected from table reads executed in other blocks 0 = Block 1 (001000-001FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit (PIC18F1320 Block 0 (00200-000FFFh) not protected from table reads executed in other blocks 0 = Block 0 (00200-000FFFh) protected from table reads executed in other blocks ...
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... REGISTER 19-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1220/1320 DEVICES R DEV2 DEV1 bit 7 bit 7-5 DEV2:DEV0: Device ID bits 111 = PIC18F1220 110 = PIC18F1320 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend Read-only bit -n = Value when device is unprogrammed REGISTER 19-13: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F1220/1320 DEVICES ...
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... WDT. INTRC Control WDT Counter 125 Programmable Postscaler 1:1 to 1:32,768 WDT 4 U-0 U-0 U-0 U-0 — — — — Writable bit -n = Value at POR Wake-up from Sleep WDT Reset Reset U-0 U-0 R/W-0 — — SWDTEN bit 0 2004 Microchip Technology Inc. ...
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... Peripheral Clock Program PC Counter Wake from Interrupt Event Note 1024 (approx). These intervals are not shown to scale. OST OSC PLL 2004 Microchip Technology Inc. PIC18F1220/1320 Bit 5 Bit 4 Bit 3 — WDTPS3 WDTPS2 — — — — In all other power managed modes, Two-Speed Start-up is not used ...
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... WDT time-out to occur and a subsequent device Reset. For this reason, Fail-Safe Clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. 2004 Microchip Technology Inc. ...
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... OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2004 Microchip Technology Inc. PIC18F1220/1320 19.4.3 FSCM INTERRUPTS IN POWER MANAGED MODES As previously mentioned, entering a power managed mode clears the Fail-Safe condition ...
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... Using Two-Speed Start-up” also possible to select another clock configuration and enter an alter- nate power managed mode while waiting for the primary system clock to become stable. When the new powered managed mode is selected, the primary clock is disabled. 2004 Microchip Technology Inc. ...
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... The actual locations of the bits are summarized in Table 19-3. MEMORY SIZE/DEVICE 4 Kbytes 8 Kbytes Address (PIC18F1220) (PIC18F1320) Range 000000h Boot Block Boot Block 0001FFh 000200h Block 0 Block 0 ...
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... A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading ‘0’s. Figures 19-6 through 19-8 illustrate table write and table read protection. FIGURE 19-6: TABLE WRITE (WRTn) DISALLOWED: PIC18F1320 Register Values TBLPTR = 0002FFh PC = 0007FEh PC = 0017FEh ...
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... PC = 001FFEh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’. FIGURE 19-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED: PIC18F1320 Register Values TBLPTR = 0002FFh PC = 0007FEh Results: Table reads permitted within Blockn, even when EBTRBn = 0. ...
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... Debugger module available from Microchip, or one of the third party development tool companies (see the note fol- lowing Section 19.7 “In-Circuit Serial Programming” for more information). and 2004 Microchip Technology Inc. Notes Shared with T1OSC – protect crystal Shared with T1OSC – protect crystal Optional – ...
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... When LVP is enabled, externally pull the PGM pin allow normal program SS execution. 2004 Microchip Technology Inc. PIC18F1220/1320 If Low-Voltage Programming mode will not be used, the LVP bit can be cleared and RB5/PGM/KBI1 becomes available as the digital I/O pin RB5. The LVP bit may be ...
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... PIC18F1220/1320 NOTES: DS39605C-page 190 2004 Microchip Technology Inc. ...
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... The desired FSR register to load the literal value into (specified by ‘f’) • No operand required (specified by ‘—’) 2004 Microchip Technology Inc. PIC18F1220/1320 The control instructions may use some of the following operands: • A program memory address (specified by ‘n’) • ...
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... ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. C, DC, Z, OV, N Optional Contents Assigned to. Register bit field. < > In the set of. User defined term (font is Courier). italics DS39605C-page 192 Description ’). the recommended form of use for compatibility with all 2004 Microchip Technology Inc. ...
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... Control operations CALL, GOTO and Branch operations 15 OPCODE 1111 n = 20-bit immediate value 15 OPCODE Fast bit OPCODE 15 OPCODE 2004 Microchip Technology Inc. PIC18F1220/1320 Example Instruction ADDWF MYREG (FILE #) 0 f (Source FILE #) MOVFF MYREG1, MYREG2 0 f (Destination FILE #) (FILE #) BSF MYREG, bit, B ...
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... Microchip Technology Inc. Status Notes Affected C, DC DC None 4 None 4 None DC None None DC, Z, OV, N ...
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... This ensures that all program memory locations have a valid instruction the table write starts the write cycle to internal memory, the write will continue until terminated. 2004 Microchip Technology Inc. PIC18F1220/1320 16-Bit Instruction Word ...
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... None kkkk kkkk C, DC, Z, OV, N kkkk kkkk Z, N kkkk kkkk None 0000 1000 None 0000 1001 None 0000 1010 None 0000 1011 None 0000 1100 None 0000 1101 None 0000 1110 None 0000 1111 2004 Microchip Technology Inc. ...
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... Q Cycle Activity Decode Read Process literal ‘k’ Data Example: ADDLW 0x15 Before Instruction W = 0x10 After Instruction W = 0x25 2004 Microchip Technology Inc. PIC18F1220/1320 ADDWF k Syntax: Operands: Operation: kkkk kkkk Status Affected: Encoding: Description: Q4 Words: Write to W Cycles: Q Cycle Activity: Q1 Decode Example: ...
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... AND literal with W [ label ] ANDLW 255 (W) .AND 0000 1011 kkkk kkkk The contents of W are AND’ed with the 8-bit literal ‘k’. The result is placed Read literal Process Write to W ‘k’ Data ANDLW 0x5F = 0xA3 = 0x03 2004 Microchip Technology Inc. ...