VSC8211XVW Vitesse Semiconductor Corp, VSC8211XVW Datasheet
VSC8211XVW
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VSC8211XVW Summary of contents
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... Auto-media Sense detects and configures to support fiber or copper VMDS-10105 Revision 4.1 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • E-mail: prodinfo@vitesse.com October 2006 SerDes mode, the VSC8211 may be used to connect a MAC either to copper media (MAC to Cat- 1000BASE-X optical module (MAC-to-Optics) ...
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Features • User-configurable copper or fiber link selection preference with programmable interrupt and signal detect I/O pins • Compliant with IEEE 802.3 (10BASE-T, 100BASE-TX, 1000BASE-T, 1000BASE-X, 100BASE-FX) and SFP MSA specifications • Over 150m of Category-5 reach with industry’s highest ...
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Application Diagrams GMIII / MII, RGMII, 10/100/1000 TBI, RTBI Mbps Ethernet MAC MDC, MDIO Station Manager Figure 1. Parallel MAC to Cat-5, Fiber Optics, or Backplanes 10/100/1000 Mbps Serial I/F Ethernet MAC MDC, MDIO Station Manager Figure 2. Serial ...
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Single mode SerDes I/F 1000BASE-LX Fiber 1000BASE-SX Multi-mode Optical Module Fiber Optional I/F for Configuration Figure 4. Media Converter (1000BASE-X to Cat-5) VMDS-10105 Revision 4.1 October 2006 3.3 V 1.2 V Quad VSC8211 Transformer Module Optional EEPROM 4 of 165 ...
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Contents 1 General Description .........................................................................................................................................................1 2 Features and Benefits .....................................................................................................................................................1 3 Applications ......................................................................................................................................................................2 4 Application Diagrams ......................................................................................................................................................3 5 Relevant Specifications & Documentation ............................................................................................................... 14 6 Datasheet Conventions ................................................................................................................................................ 15 7 Document History and Notices ................................................................................................................................... 16 8 Device Block Diagram ...
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Twisted Pair Interface ................................................................................................................................................... 43 11.1 Twisted Pair Autonegotiation (IEEE802.3 Clause 28) ........................................................................ 43 11.2 Twisted Pair Auto MDI/MDI-X Function .............................................................................................. 44 11.3 Auto MDI/MDI-X in Forced 10/100 Link Speeds ................................................................................. 44 11.4 Twisted Pair Link Speed Downshift .................................................................................................... ...
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Hardware Configuration Using CMODE Pins ........................................................................................................... 66 19.1 Setting the CMODE Configuration Bits ............................................................................................... 66 19.2 CMODE Bit descriptions ..................................................................................................................... 66 19.3 Procedure For Selecting CMODE Pin Pull-up/Pull-down Resistor Values ......................................... 71 20 EEPROM Interface ........................................................................................................................................................ 72 20.1 Programming ...
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Register 20 (14h) – Reserved .............................................................................................................105 25.3.22 Register 21 (15h) – Reserved .............................................................................................................105 25.3.23 Register 22 (16h) – Control & Status Register ..................................................................................106 25.3.24 Register 23 (17h) – PHY Control Register #1 ...................................................................................108 25.3.25 Register 24 (18h) – PHY ...
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SerDes Specifications ................................................................................................................................................ 144 30 System Timing Specifications .................................................................................................................................. 145 30.1 GMII Mode Transmit Timing (1000BASE-T) ..................................................................................... 145 30.2 GMII Mode Receive Timing (1000BASE-T) ...................................................................................... 146 30.3 MII Transmit Timing (100Mbps) ........................................................................................................ 147 30.4 MII Receive Timing (100Mbps) ......................................................................................................... ...
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Figures Figure 1. Parallel MAC to Cat-5, Fiber Optics, or Backplanes.............................................................................. 3 Figure 2. Serial MAC to Cat-5, Fiber Optics, or Backplanes ................................................................................ 3 Figure 3. GBIC/SFP Serial Interface (SGMII or 802.3z SerDes to Cat-5) ............................................................ 3 Figure 4. Media ...
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Figure 41. TBI Transmit AC Timing..................................................................................................................... 148 Figure 42. TBI Receive AC Timing ..................................................................................................................... 149 Figure 43. RGMII/RTBI Uncompensated AC Timing and Multiplexing ............................................................... 151 Figure 44. RGMII/RTBI Compensated AC Timing and Multiplexing ................................................................... 152 Figure 45. JTAG Interface AC ...
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Tables Table 1. Signal Type Description ......................................................................................................................... 20 Table 2. Configuration and Control Signals ......................................................................................................... 21 Table 3. System Clock Interface Signals (SCI) .................................................................................................... 22 Table 4. Analog Bias Signals ............................................................................................................................... 23 Table 5. JTAG Access Port .................................................................................................................................. 23 Table ...
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Table 41. Thermal Specifications - 117 ball LBGA 10x14mm package ............................................................... 135 Table 42. VDDIO @ 3.3V, RGMII-CAT5, 1000BASE-T, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off ............................................................................................................................................... 136 Table 43. VDDIO @ 3.3V, RGMII-100BASE-FX, FDX, 1518 ...
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Relevant Specifications & Documentation The VSC8211 conforms to the following specifications. Please refer to these documents for additional information. Specification - Revision Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications. IEEE 802.3-2002 consolidates ...
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Datasheet Conventions Conventions used throughout this datasheet are specified in the following table. Convention Syntax RegisterNumber.Bit Register or number RegisterNumber.BitRange Extended RegisterNumberE.Bit Page Regis RegisterNumberE.BitRange ter Number Signal name SIGNALNAME (active high) Signal name SIGNALNAME (active low) ...
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Document History and Notices Revision Date Number 0.1.0 Feb 0.1.1 May 11 04 2.0 July 08 04 4.0 August 17 05 4.1 October 2006 VMDS-10105 Revision 4.1 October 2006 Comments First Preliminary Release Updated pin description with ...
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Device Block Diagram The diagram below depicts the primary functional blocks and pins for the VSC8211. SDOP SerDes SDON SGMII SDIP TBI or SDIN Serial PCS TDP I/O TDN PCS RDP ENCODER RDN TBI PAM-5 SYMBOL SCLKP MAPPER, SCLKN ...
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Package Pin Assignments & Signal Descriptions 9.1 VSC8211 117-Ball LBGA Package Ball Diagram The following diagram shows the view from the top of the package with underlying BGA ball positions superimposed ...
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LBGA Ball to Signal Name Cross Reference TXEN GTXCLK TXCLK RXER B TXD1 TXDO TXER COL C TXD3 TXD2 VDDIOMAC CRS D TXD5 TXD4 VDDIOMAC VSS E TXD7 TXD6 NC VSS F SDON SDOP ...
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Signal Type Description Symbol Signal Type I Digital Input I Digital Input with Pull- Digital Input with Pull-up PU5V I Digital Input with Pull-down PD I Digital Input with Pull-down PD5V I Differential Input Pair DIFF O ...
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Detailed Pin Descriptions 9.4.1 Configuration and Control Signals 117 LBGA Signal Name Type Ball D11 CMODE7 D12 CMODE6 D13 CMODE5 E13 CMODE4 I A E12 CMODE3 E11 CMODE2 G11 CMODE1 F11 CMODE0 A12 RESET I TXDIS ...
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System Clock Interface Signals (SCI) 117 LBGA Signal Name Type BALL XTAL1/ J10 I REFCLK H10 XTAL2 O CLKOUTMICRO OSCDIS MODDEF0/ A10 O CLKOUTMAC VMDS-10105 Revision 4.1 October 2006 Table 3. System Clock Interface Signals (SCI) ...
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Analog Bias Signals 117 LBGA Signal Name Type BALL A J6 REFREXT BIAS A H6 REFFILT BIAS 9.4.4 JTAG Access Port 117 LBGA Signal Name Type BALL I A11 TDI PU5V O B11 TDO ZC I B10 TMS PU5V ...
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Serial Management Interface Signals 117 LBGA Signal Name Type BALL MODDEF1 MDC MODDEF2/ G4 I/O MDIO H4 MDINT OD VMDS-10105 Revision 4.1 October 2006 Table 6. Serial Management Interface Signals The Functionality of this pin is determined ...
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EEPROM Interface Signals 117 LBGA Signal Name Type BALL EECLK PLLMODE O H5 EEDAT ZC 9.4.7 LED Interface Signals 117 LBGA Signal Name Type BALL C13 LED4 C12 LED3 O B13 LED2 ZC B12 LED1 A13 ...
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Parallel MAC Interface Signals - Transmit Signals The following signals are used in Parallel MAC Interface PHY Operating modes and connect to the parallel data bus MAC via the industry-standard GMII, RGMII, TBI, RTBI and MII interfaces. If these ...
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Table 9. Parallel MAC Interface Signals - Transmit Signals (continued) 117 Signal Name LBGA Parallel MAC Interface Modes BALL TBI RTBI GMII TD[9] B3 TX[9] and TXER TD[4] PMAT A2 TXC GTXCLK XCLK 1 See TX_CLK pin description in following ...
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Parallel MAC Interface Signals - Receive Signals The following signals are used in Parallel MAC Interface PHY Operating modes and connect to the parallel data bus MAC via the industry-standard GMII, RGMII, TBI, RTBI and MII interfaces. If these ...
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Table 10. Parallel MAC Interface Signals - Receive Signals (continued) 117 Signal Name LBGA Parallel MAC Interface Modes BALL TBI RTBI GMII Leave Leave PMARX pins pins A3 CLK1 uncon- uncon- nected nected Leave pins A5 RX[8] RXDV uncon- nected ...
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Table 10. Parallel MAC Interface Signals - Receive Signals (continued) 117 Signal Name LBGA Parallel MAC Interface Modes BALL TBI RTBI GMII Leave COM- pins C4 CRS DET uncon- nected Leave RXCLK pins B4 COL 125 uncon- nected 9.4.10 Serial ...
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Table 11. Serial MAC/Media Interface Signals (continued) 117 Signal LBGA Type Name BALL SGMII Clock Differential Output Pair (used in SGMII to CAT5/SerDes/AMS PHY Oper- ating Modes). This signal pair is a differential 625MHz SGMII clock for the SGMII data ...
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Table 11. Serial MAC/Media Interface Signals (continued) 117 Signal LBGA Type Name BALL The functionality of this signal pin depends on the value for Extended ‘SFP Mode’ CMODE Pins” RXLOS - Receiver Loss of Signal Output (valid in SFP Mode, ...
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Twisted Pair Interface Signals 117 Signal LBGA Type Name BALL TX/RX Channel “A” Positive Signal. Positive differential signal connected to the positive primary side of the transformer. This signal forms the positive signal of the “A” data channel. In ...
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Power Supply and Ground Connections Table 13. Power Supply and Ground Connections 117 LBGA Supply Recommended PCB BALL Name Power Plane Digital I/O Power Supply Pins 1 C6, C3, D3 VDDIOMAC 1 G7 VDDIOMICRO 1 D10 VDDIOCTRL Digital Core ...
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Power Supply and Associated Functional Signals Table 15. Power Supply and Associated Functional Signals Power Nominal Voltages Supply Pins RXLOS/SIGDET, RXD[7:0], RXDV, RXER, RXCLK, COL, CRS, TXCLK, TXER, GTX- VDDIOMAC 3.3V or 2.5V CLK, TXEN, TXD[7:0], MODDEF0/CLKOUTMAC EECLK/PLLMODE, EEDAT, ...
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System Schematics 10.1 Parallel Data MAC to CAT5 Media PHY Operating Mode CLKIN RXLOS/SIGDET U2 GMII/MII/RGMII/TBI/RTBI MAC VDD U3 TDI VDDIOCTRL TDO TMS JTAG Port Controller TCK TRST RESET VDDIOMICRO VDDIOMICRO U4 SDA SCL EEPROM VDDIOMICRO or VDDIOMICRO VDDIOMICRO ...
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Parallel Data MAC to 1000Mbps Fiber Media PHY Operating Mode II II ...
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Parallel Data MAC to Copper/Fiber Auto Media Sense PHY Operating Mode CLKIN U2 GMII/MII/RGMII/TBI/RTBI MAC VDD U3 TDI VDDIOCTRL TDO TMS JTAG Port Controller TCK TRST RESET VDDIOMICRO 4.7k VDDIOMICRO U4 SDA SCL EEPROM VDDIOMICRO or VDDIOMICRO VDDIOMICRO 4.7k ...
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SGMII/802.3z SerDes MAC to CAT5 Media PHY Operating Mode VDDIO M AC CLKIN RXLO S/SIG DET TDP U2 TDN S GM II/802.3z S erDes M AC Controller RDP 100 or 150 VDD RDN SCLKP 100 or 150 SCLKN U3 ...
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SGMII/802.3z SerDes to 1000Mbps Fiber Media PHY Operating Mode VDDIOMAC CLKIN RXLOS/SIG DET .01µF TDP U2 .01µF TDN SGMII/802.3z SerDes MAC Controller .01µF RDP 100 or 150 .01µF VDD RDN .01µF SCLKP 100 or 150 SCLKN .01µF U3 TDI ...
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Fiber Media Implementation LINK100/ACTIVITY LEDn PHY_TXVNB TXVNB PHY_TXVPB TXVPB PHY_TXVPA TXVPA PHY_TXVNA TXVNA TXVPC TXVNC TXVPD TXVND VSC8211/VSC8221 Figure 13. System Schematic – ‘100Mbps Fiber Media’ Implementation VMDS-10105 Revision 4.1 October 2006 VDD33 SFP_RD- SFP_RD+ SFP_TD+ SFP_TD- VDD33 ...
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Serial MAC to Fiber/CAT5 Media PHY Operating Mode VDDIOMAC CLKIN RXLOS/SIGDET .01µF TDP U2 .01µF TDN SGMII/802.3z SerDes MAC Controller RDP .01µF .01µF VDD RDN .01µF SCLKP (Optional - May not be required by the MAC) SCLKN .01µF U3 ...
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Twisted Pair Interface The twisted pair interface on the VSC8211 is fully compliant with the IEEE802.3-2000 specification for CAT-5 media. All passive components necessary to connect the PHY to an external 1:1 transformer have been integrated into the VSC8211. ...
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Twisted Pair Auto MDI/MDI-X Function For trouble-free configuration and management of Ethernet links, the VSC8211 includes robust Automatic Crossover Detection functionality for all three speeds on the twisted pair interface (10BASE-T, 100BASE-TX, and 1000BASE-T) – fully compliant with the ...
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Write MII Register 8 = 0x0212 • Write MII Register 31 = 0x52B5 • Write MII Register 2 = 0x0012 • Write MII Register 1 = 0x3003 • Write MII Register 0 = 0x87FA • Write MII Register 31 ...
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The MODDEF1/MDC, MODDEF2/MDIO, and the MDINT pins comprise the SMI interface. By writing to MII Register 21E.15 at startup (Refer to "EEPROM Interface" for details), the SMI of the PHY can be set to operate in one of the following ...
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MODDEF1 MODDEF2 START M O DDEF1 MODDEF2 START MODDEF1 MODDEF2 START VMDS-10105 Revision 4.1 October 2006 Figure 17. Start [S] and Stop ...
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Write Operation - Random Write • R4..R0 are the 5 bits of the Register address R. • M7..M0 are ...
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Write Operation - Sequential Write LSB for Register LSB for Register R LSB for Register R • ...
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Read Operation - Random Read • R4..R0 are the 5 bits of the Register address • M7..M0 are bits ...
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Read Operation - Sequential Read LSB for Register LSB for Register R LSB for Register R+n ...
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PHY Register Access with SMI in IEEE Mode In IEEE mode, the SMI is fully compliant with the IEEE 802.3-2000 MII Interface specifications. In IEEE mode, the SMI pins function as follows: Pin Name MDC Clock Input, 0 – ...
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The following two figures diagram IEEE SMI read and IEEE SMI write operations tio riv ...
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LED Interface The PHY has five dedicated LED[4:0] pins to drive 5 LEDs directly. For power savings, all LED outputs can be configured to pulse at 5kHz with a 20% duty cycle. All LED outputs are active-low and driven ...
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Function Name State Link100/Activity Pulse-stretch/Blink Link10/Activity Pulse-stretch/Blink 1 Link10/100 Activity Pulse-stretch/Blink 1 Link100/1000 Activity Pulse-stretch/Blink Link/Act Pulse-stretch/Blink 1 Collision Pulse-stretch/blink 1 Activity Pulse-stretch/blink 1 Fiber 0 1 ...
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In addition to function selection, several options are available for the LED outputs through the use of MII register 27.5:0. These are summarized below: MII LED Option Bits Reg Bits 5:4 LED Blink/Pulse-Stretch Rate 3 LED pulse-stretch/blink 2 LED Pulsing ...
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Test Mode Interface (JTAG) The PHY supports the Test Access Port and Boundary Scan Architecture IEEE 1149.1 standards. The device includes an IEEE 1149.1 compliant test interface, often referred “JTAG TAP Interface”. IEEE 1149.1 defined test ...
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The PHY also includes the optional Device Identification Register, shown in the following table, which allows the manufacturer, part number, and version number of the device to be determined through the TAP Controller. See Chapter 11 of the IEEE 1149.1-1990 ...
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It also allows data values to be loaded into the boundary-scan cells prior to the selection of other boundary-scan test instructions. IDCODE The optional IDCODE instruction provides the version number (bits 31:28), and Vitesse’s manufacturer identity (bits11:1), ...
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Enhanced ActiPHY Power Management In addition to the IEEE-specified power-down control bit power management mode. This mode enables support for power-sensitive applications such as laptop computers with Wake- on-LAN™ capability. It utilizes a signal-detect function that monitors the media ...
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Low power state In the low power state, all major digital blocks are powered down. However the following functionality is provided: • SMI interface (MDC/MODDEF1, MDIO/MODDEF2, MDINT) • CLKOUTMAC and CLKOUTMICRO In this state, the PHY monitors the media ...
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Ethernet In-line Powered Device Support 17.1 Cisco In-Line Powered Device Detection This feature is used for detecting in-line powered devices in Ethernet network applications. The VSC8211's in-line powered device detection mode can be part of a system that allows ...
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The PHY monitors for the special FLP signal looped back by the LP device capable of receiving in-line power will loop back the special FLP pulses when powered-down state. This is reported when ...
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Advanced Test Modes 18.1 1000BASE-T Ethernet Packet Generator (EPG) For system-level debugging and in-system production testing, the VSC8211 includes an Ethernet packet generator. This can be used to isolate problems between the MAC and PHY and between a local ...
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Link Partner CAT-5 or Fiber 18.5 Connector Loopback Connector Loopback allows for the twisted pair interface to be looped back externally. In this mode the PHY must be connected to a loopback connector or a loopback cable. For this loopback, ...
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Hardware Configuration Using CMODE Pins Each of the eight CMODE pins (CMODE[7:0]) are used to latch a four bit value at PHY reset. A total of thirty two CMODE configuration bits are set at reset. Each CMODE bit represents ...
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Table 26. CMODE Bit to PHY Operation Condition Parameter Mapping CMODE Pin Name Bit 3 CMODE0 PHY Address[3] CMODE1 SFP Mode Disable CMODE2 PHY Operating Mode[3] PHY Operating Mode[2] PHY Operating Mode[1] PHY Operating Mode[0] CMODE3 LED Control[1] CMODE4 LED ...
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Each of the PHY Operating Condition Parameters mentioned in the Table 26 above is described in detail in Table 27. Table 27. PHY Operating Condition Parameter Description PHY Operating CMODE Pin Name and Bit Condition Parameter Position Name PHY Address[4:0] ...
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Table 27. PHY Operating Condition Parameter Description (continued) PHY Operating CMODE Pin Name and Bit Condition Parameter Position Name Link/Activity and Linkxxxx/Activity CMODE7[3] behaviour RGMII/RTBI Transmit Path CMODE5[3:2] Timing Compensation[1:0] RGMII/RTBI Receive Path CMODE5[1:0] Timing Compensation[1:0] Auto-negotiation Advertisement CMODE3[0],CMODE4[1] Control[1:0] ...
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Table 27. PHY Operating Condition Parameter Description (continued) PHY Operating CMODE Pin Name and Bit Condition Parameter Position Name SFP Mode Disable CMODE1[3] SIGDET pin CMODE1[1] direction SerDes Line CMODE1[0] Impedance SQE Enable CMODE3[2] 10BASE-T Echo On CMODE3[1] MII Register ...
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Table 27. PHY Operating Condition Parameter Description (continued) PHY Operating CMODE Pin Name and Bit Condition Parameter Position Name SIGDET pin Polarity CMODE6[2] Enhanced CMODE6[1] TM ActiPHY Enable CLKOUTMICRO Fre- CMODE6[0] quency Link Speed Auto- CMODE7[2] Downshift Enable 19.3 Procedure ...
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EEPROM Interface The EEPROM Interface consists of the EEDAT and EECLK pins of the PHY. If this interface is used, these pins should connect to the SDA and SCL pins respectively of a serial EEPROM that is compatible with ...
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Programming Multiple VSC8211s Using the Same EEPROM To prevent contention on the 2 wire bus when multiple PHYs use the same EEPROM for initialization, the EEPROM start-up block of each VSC8211 monitors the bus for (PHY Address[4: ...
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Table 28. Configuration EEPROM Data Format (continued) Address ------------- ------------- ------------- ------------- M+7 M+6 M+5 M+4 M+3 M+2 M+1 {bpage_addr2,s_ addr2 ------------- N+7 N+6 N+5 N+4 N+3 N+2 N+1 {bpage_addr1,s_ addr1 ------------- 7,263,519,.. 6,262,518,.. 5,261,517,.. 4,260,516,.. ...
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PHY Startup and Initialization The PHY Startup and Initialization sequence is detailed in the flowchart below ...
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PHY Operating Modes The PHY Operating Mode is set according to the value of Configuration Using CMODE Pins" and startup. The following table summarizes the PHY operating modes. MII Operating Register CMODE2 Mode 23.15:12,2 [3:0] Category 3.2:1 0011, 10 ...
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Serial MAC to Serial Media PHY Operating Mode: In this mode, the high-speed serial data on the SDIP/SPIN input pins is routed to the RDP/RDN output pins and data from the TDP/TPN input pins is routed to the SDOP/SDON ...
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Extended MII Register 16E bits 2:1, the Remote Fault Mapping Mask, and bit 0, the Remote Fault Mapping OR, handle remote fault mapping. For more information, see 123. The functionality of these bits is summarized in the following tables: Table ...
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Table 33. Clause 37 Autonegotiation Link Partner Remote Fault Bits Bit 16E.0, LP Remote 16E.2:1, Remote 1 Remote Fault Bits Fault OR Fault Mask 01 01 ...
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PHY Register Set Conventions The user can control the PHY's features, operating modes, etc. by setting the PHY Registers to the desired values. The PHY provides access to its Registers via the Serial Management Interface. For details on PHY ...
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PHY's Register Set Nomenclature Register Address 0-15 16-31 16-31 24.3 PHY Register Bit Types PHY Register bit types are defined in the table below: Register Bit Type R/W Read and Write, effective immediately RO Read Only (must be written ...
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PHY Register Set 25.1 Clause 28/37 Resister View PHY registers 0 through 15 are implemented according to the IEEE 802.3 specification. According to this standard, the contents of MII Registers and 10 are different for ...
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PHY Register Names and Addresses Table 34. PHY Register Names and Addresses Register Name Mode Control Mode Status PHY Identifier Register # 1 PHY Identifier Register # 2 Auto-Negotiation Advertisement Auto-Negotiation Link Partner Ability Auto-Negotiation Expansion Auto-Negotiation Next-Page Transmit ...
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Table 34. PHY Register Names and Addresses (continued) Register Name Reserved Reserved Reserved 1000BASE-T Ethernet Packet Generator (EPG 1000BASE-T Ethernet Packet Generator (EPG VMDS-10105 Revision 4.1 October 2006 Register Address Register Number 26E 27E 28E 29E ...
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MII Register Descriptions 25.3.1 Register 0 (00h) – Mode Control Register - Clause 28/37 View Register 0 (00h) – Mode Control Register - Clause 28/37 View Bit Name 1 15 Software Reset 14 Near End Loopback 6, 13 Forced ...
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Auto-Negotiation Enable After a power-up, or reset, the PHY automatically activates the Auto-Negotiation state machine, setting bit 0. “1” “0” is written to bit 0.12, the Auto-Negotiation process is disabled and the present contents ...
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Register 1 (01h) – Mode Status Register - Clause 28/37 View Bit Name 3 Auto-Negotiation Capability 2 Link Status 1 Jabber Detect 0 Extended Capability 1.15 – 100BASE-T4 Capability The VSC8211 is not 100BASE-T4 capable, so this bit is hard-wired ...
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Auto-Negotiation Capability The VSC8211 is Auto-Negotiation capable, so this bit is hard-wired to “1”. Note that this bit will read a “1” even if Auto- Negotiation is disabled via bit 0.12. 1.2 – Link Status This bit will ...
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Vendor Revision Number The current Revision Number of this IC is ‘0001’. 25.3.5 Register 4 (04h) – Auto-Negotiation Advertisement Register 25.3.5.1 Clause 28 View Register 4 (04h) – Auto-Negotiation Advertisement Register - Clause 28 View Bit Name 15 ...
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Advertise Capability Bits 4.9:5 allow the user to customize the ability information transmitted to the Link Partner during auto-negotiation. By writing a “1” to any of these bits, the corresponding ability will be advertised to the Link Partner. ...
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Advertise 1000BASE-X Capability Bits 4.6:5 control the 1000BASE-X capability advertisement transmitted to the link partner for both fiber and copper media. Changing these bits in Clause-37 view will also change MII Register bits 9.9:8 in Clause-28 view. 4.4:0 ...
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LP Advertise Capability Bits 5.9:5 reflect the abilities of the Link Partner. A “1” on any of these bits indicates that the Link Partner advertises capability of performing the corresponding mode of operation. These bits are not available ...
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Reserved 25.3.7 Register 6 (06h) – Auto-Negotiation Expansion Register 25.3.7.5 Clause 28 View Register 6 (06h) – Auto-Negotiation Expansion Register - Clause 28 View Bit Name 15:5 Reserved 4 Parallel Detection Fault 3 LP Next-Page Able 2 Local ...
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Reserved 6.2 – Local PHY Next-Page Able The VSC8211 is not next-page capable in Clause-37 auto-negotiation, therefore this bit is hard-wired to “0”. Note that this does not apply to bit 6.2 in Clause-28 auto-negotiation. 6.1 - Page ...
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The Message/Unformatted Code bits indicate the message code being transmitted to the Link Partner. The local PHY passes the message code to the Link Partner without interpreting or reacting to it. By default, this code is set to “000 0000 ...
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Register 9 (09h) – 1000BASE-T Control Register 1 25.3.10.7 Clause 28 View Register 9 (09h) – 1000BASE-T Control Register - Clause 28 View Bit Name 15:13 Transmitter Test Mode MASTER/SLAVE Manual 12 Configuration Enable MASTER/SLAVE Manual 11 Configuration Value ...
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Test Mode 3: The PHY transmits the data symbol sequence {+2, -2} repeatedly on all channels. The transmitter should use a 125.00 MHz ± 0.01% clock and should operate in SLAVE timing mode. • Test Mode 4: The PHY ...
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Auto-Negotiation. After Auto-Negotiation is complete, changing the state of this bit has no effect unless Auto-Negotiation is manually restarted. 1 9.8 – 1000BASE-T HDX Since the VSC8211 is 1000BASE-T HDX capable, this bit is “1” ...
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MASTER/SLAVE Configuration Fault This bit indicates whether a MASTER/SLAVE configuration fault has been detected by the local PHY. A configuration fault occurs if both the local and remote PHYs are forced to the same MASTER/SLAVE state ...
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Clause 37 View Register 10 (0Ah) - 1000BASE-T Status Register #1 - Clause 37 View Bit Name 15:0 Reserved 9.15:0 - Reserved In Clause-37 register view, MII register 10 is reserved. Note that MII register 10 bits in Clause-28 ...
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Reserved 25.3.16 Register 15 (0Fh) – 1000BASE-T Status Register #2 25.3.16.11 Clause 28 View Register 15 (0Fh) – 1000BASE-T Status Register #2 - Clause 28 View Bit Name 15 1000BASE-X FDX Capability 14 1000BASE-X HDX Capability 13 1000BASE-T ...
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Capability In Clause-37 view, bits 15.15:12 differ from bits 15.15:12 in Clause-28 view by their reset values only. In Clause 37 view Register 15.15:12 = ‘0011’. 15:11:0 - Reserved 25.3.17 Register 16 (10h) – Reserved Register 16 ...
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Register 18 (12h) – Bypass Control Register Register 18 (12h) – Bypass Control Register Bit Name 15 Reserved 14 Bypass 4B5B Encoder/Decoder R/W 13 Bypass Scrambler 12 Bypass Descrambler 11:9 Reserved 8 Transmitter Test Clock Enable 7:6 Reserved Disable ...
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Reserved 18.8 – Transmitter Test Clock Enable When a “1” is written to bit 18.8, the CLKOUTMICRO output pin becomes a test pin for the transmit clock “TXCLK”. This capability is intended to enable measurement of transmitter timing ...
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Register 19 (13h) – Reserved Register 19 (13h) – Reserved Bit Name 15:0 Reserved 19.15:0 - Reserved 25.3.21 Register 20 (14h) – Reserved Register 20 (14h) – Reserved Bit Name 15:0 Reserved 20.15:0 – Reserved 25.3.22 Register 21 (15h) ...
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Register 22 (16h) – Control & Status Register Register 22 (16h) – Control & Status Register Bit Name 15 Disable Link Integrity State Machine R/W 14 Disable jabber Detect 13 Disable 10BASE-T Echo 12 SQE Disable Mode 11:10 10BASE-T ...
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Squelch Control When bits 22.11:10 are set to “00”, the VSC8211 uses the squelch threshold levels prescribed by the IEEE’s 10BASE-T specification. When bits 22.11:10 are set to “01”, the squelch level is decreased, which may improve ...
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Register 23 (17h) – PHY Control Register #1 Register 23 (17h) – PHY Control Register #1 Bit Name 15:12 MAC/Media Interface Mode Select RWSW 11:10 RGMII/RTBI TXC Skew Selection 9:8 RGMII/RTBI RXC Skew Selection R/W 7 EWRAP Enable 6 ...
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MAC/Media Interface Mode Select Bits 23.15:12 and 23.2:1 are used to select the MAC interface modes and media interface modes. The reset value for these bits is dependent upon the state of the MAC Interface bits in the ...
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PCB trace skews. The default values of these bits are specified by the RGMII Skew bits in the CMODE hardware configuration. See Table 27, information. 23.7 – EWRAP Enable When bit 23.7 is set ...
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Register 24 (18h) – PHY Control Register #2 Register 24 (18h) – PHY Control Register #2 Bit Name 1 15:13 Reserved 2 12 Enable PICMG Miser Mode 11:10 Reserved TX FIFO Depth Control for RGMII, 9:7 SGMII and Serial ...
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RX FIFO Depth Control Used in 1000BT Serial MAC, SGMII, and RTBI modes only, bits 24.6:4 control symbol buffering as determined by the receive synchronization FIFO. An internal FIFO is used to synchronize the clock domains between ...
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Register 25 (19h) – Interrupt Mask Register Register 25 (19h) – Interrupt Mask Register Bit Name 15 Interrupt Pin Enable 14 Reserved 13 Link State-Change 12 Reserved Auto-Negotiation Error Interrupt 11 Mask Auto-Negotiation-Done / Interlock 10 Done Interrupt Mask ...
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Auto-Negotiation Error Interrupt Mask When bit 25.11 is set to “1”, the Auto-Negotiation Error Interrupt is enabled. 25.10 – Auto-Negotiation-Done / Interlock Done Interrupt Mask When bit 25.10 is set to “1”, the Auto-Negotiation-Done / Interlock Done Interrupt ...
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Register 26 (1Ah) – Interrupt Status Register Register 26 (1Ah) – Interrupt Status Register Bit Name 15 Interrupt Status 14 Reserved 13 Link State-Change Interrupt Status 12 Reserved 11 Auto-Negotiation Error Interrupt Status Auto-Negotiation-Done / Interlock Done 10 Interrupt ...
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Symbol Error Interrupt Status When a symbol error is detected by the descrambler, bit 26.8 is set to “1” if bit cleared when read. 26.7 – Descrambler Lock-Lost Interrupt Status When the descrambler loses lock, bit 26.7 is ...
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Register 27 (1Bh) – LED Control Register Register 27 (1Bh) – LED Control Register Bit Name 15:14 LED Pin 4 Configuration 13:12 LED Pin 3 Configuration 11:10 LED Pin 2 Configuration 9:8 LED Pin 1 Configuration 7:6 LED Pin ...
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LED Pin Configuration Each of the five LED pins on each port of the VSC8211 can be configured for one of four functions. These functions are different for each LED pin. Bits 27.15:6 are used to select ...
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Register 28 (1Ch) – Auxiliary Control & Status Register Register 28 (1Ch) – Auxiliary Control & Status Register Bit Name 15:7 Reserved 6 Enhanced ActiPHY Mode Enable 5 FDX Status 4:3 Speed Status 1 2 Reserved TM 1:0 Sleep ...
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Register 29 (1Dh) – Reserved Register 29 (1Dh) – Reserved Bit Name 15:0 Reserved 29.15:0 - Reserved 25.3.31 Register 30 (1Eh) - MAC Interface Clause 37 Autonegotiation Control & Status Register 30 (1Eh) – MAC Interface Clause 37 Autonegotiation ...
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MAC Asymmetric Pause Bit 30.11 corresponds to the Asymmetric Pause bit sent to the VSC8211 by the MAC during the clause 37 auto-negotiation process. 30.10 - MAC Symmetric Pause Bit 30.10 corresponds to the Symmetric Pause bit sent ...
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Register 31 (1Fh) – Extended Page Access Register 31 (1Fh) – Extended Page Access Bit Name Access 15:1 Reserved RO 0 Extended Page Access R/W 31.15:0 – Reserved 31.0 - Extended Page Access In order to provide additional functionality ...
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Extended MII Registers 25.4.1 Register 16E (10h) - Fiber Media Clause 37 Autonegotiation Control & Status Register 16E (10h) – Fiber Media Clause 37 Autonegotiation Control & Status Bit Name 15:14 Reserved 13:12 Fiber Remote Fault 11 Fiber Asymmetric ...
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Fiber Full Duplex Bit 16E.8 corresponds to the Full Duplex Ability bit sent to the VSC8211 by the fiber link partner during the clause 37 auto- negotiation process. 16E.7 - Fiber Half Duplex Bit 16E.7 corresponds to the ...
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Hysteresis Disable When set, this bit disables the 25mv Hysteresis built into the TDP/TDN and SDIP/SDIN high speed differential input pins. This bit is clear by default in parallel MAC to CAT5/AMS category of PHY Operating modes. ...
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Register 20E (14h) - Extended PHY Control Register #3 Register 20E (14h) – Extended PHY Control Register #3 Bit Name 15 Disable Byte Sync 1 14 Reserved 13 Enable LED force 12:10 SDOP/SDON Output swing Control R/W SDOP/SDON and ...
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SDOP/SDON and SDIP/SDIN line impedance These bits set the line impedance of the SDOP/SDON and SDIP/SDIN pins to 50Ω or 75Ω single ended (100Ω or 150Ω differential). 20E.8 - CLKOUTMICRO Frequency The frequency of the CLKOUTMICRO pin can be ...
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Register 21E (15h) - EEPROM Interface Status and Control Register Register 21E (15h) - EEPROM Interface Status and Control Register Bit Name 15 SFP MODE Re-read EEPROM on Software 14 Reset 13 EEPROM Access Enable 12 EEPROM Read/Write 11 ...
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EEPROM Address These bits contain the EEPROM address that the VSC8211 will read from or write to when bit 21E.13 is set. 25.4.7 Register 22E (16h) - EEPROM Data Read/Write Register Register 22E (16h) - EEPROM Data Read/Write ...
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CRC Counter When the Ethernet Packet Generator is enabled, these bits count the number of packets received that contain a CRC error. This counter will saturate at 0FFh and is cleared when read. 25.4.9 Register 24E (18h) - ...
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Reserved 25.4.14 Register 29E (1Dh) - 1000BASE-T Ethernet Packet Generator (EPG) Register #1 Register 29E (1Dh) - 1000BASE-T Ethernet Packet Generator (EPG) Register #1 Bit Name 15 EPG Enable 14 EPG Run/Stop 13 Transmission Duration 12:11 Packet Length ...
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Destination Address The 6-byte destination address for packets generated by the EPG is assigned one of 16 values in the range 0xF0 FFh through 0xFF FFh. The most significant byte’s ...
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Electrical Specifications 26.1 Absolute Maximum Ratings Stresses listed under the Absolute Maximum Ratings may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these ...
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Recommended Operating Conditions Symbol Min Typ VDD33A 3.0 3.3 VDDIOMAC/ 3.0 3.3 VDDIOMICRO/ 2.25 2.5 VDDIOCTRL VDD12 1.14 1.2 VDD12A 1.14 1 REFCLK 125 F -100 TOL (REFCLK) F -1500 TOL (LINK) R 2.00 EXT C 0.1 ...
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Thermal Application Data Printed Circuit Board Conditions (JEDEC JESD51-9) PCB Layers PCB Dimensions (mm x mm) PCB Thickness (mm) Environment Conditions Maximum operation junction temperature (ºC) Ambient free-air operating temperature (ºC) Worst Case Power Dissipation (W) Symbol Min θ ...
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Current and Power Consumption Power supply current and power consumption information is provided below for PCB design targets. A maximum margin of ±20% from typical should be included to account for variation in the specified power supply voltage ranges, ...
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Table 45. VDDIO @ 3.3 V, RGMII-CAT5, 100BASE-TX, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off Symbol Min I 86 VDD33A I 16 VDDIOMAC I 0.5 VDDIOCTRL I 0.5 VDDIOMICRO I 92 VDD12 I 24 VDD12A P ...
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Table 47. VDDIO @ 3.3 V, RGMII-CAT5, 10BASE-T, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off Symbol Min I 146 VDD33A I 11 VDDIOMAC I 0.5 VDDIOCTRL I 0.5 VDDIOMICRO I 27.5 VDD12 I 24 VDD12A P ...
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Table 49. VDDIO @ 3.3 V, RGMII-Fiber, 1000BASE-X, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off Symbol Min I 17 VDD33A I 44 VDDIOMAC I 0.5 VDDIOCTRL I 0.5 VDDIOMICRO I 51.5 VDD12 I 20 VDD12A P ...
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Table 51. VDDIO @ 3.3 V, SerDes-CAT5, 1000BASE-T, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off Symbol Min I 108 VDD33A I 11 VDDIOMAC I 0.5 VDDIOCTRL I 0.5 VDDIOMICRO I 308 VDD12 I 34 VDD12A P ...
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DC Specifications 27.1 Digital Pins (VDDIO = 3.3V) The following specifications are valid only when T Table 54. Digital Pins Specifications (VDDIO = 3.3 V) Symbol Min Typ V 2 GND ...
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LED Output Pins (LED[4:0]) The following specifications are valid over a voltage range of 2.3v to 1.3v applied to the LED[4:0] pins. Symbol Max I 40 sinking 1 This recommendation is purely from a power savings view point. 28 ...
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Crystal Option The following component specifications should be used to select a crystal for use with the VSC8211. For more information about clocking and frequency offset tolerance specifications when jumbo packet support is required, see the application note Using ...
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SerDes Specifications The following specifications are valid over the recommended operating conditions listed in Symbol Min T_lock Vidiff 100 Vodiff 350 Vicm 0.437 x VDD12 .45 x VDD12 0.464 x VDD12 Vocm 0.4 x VDD12 .45 x VDD12 Tr_HS ...
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System Timing Specifications 30.1 GMII Mode Transmit Timing (1000BASE-T) For GMII mode, the following specifications are valid when the I/O power supply (VDDIOMAC) is 2.5V or 3.3V, ±10%, and the MAC/Media Interface Mode Select bits (see been set to ...
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GMII Mode Receive Timing (1000BASE-T) For GMII mode, the following specifications are valid when the I/O power supply (VDDIOMAC) is 2.5V or 3.3V, ±10%, and the MAC/Media Interface Mode Select bits (see page 129) have been set to GMII ...
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MII Transmit Timing (100Mbps) The following specifications are valid when the I/O power supply (VDDIOMAC) is 2.5V or 3.3V, ±10%, the MAC/Media Interface Mode Select bits (see section 25.4.8 “Register 23E (17h) - Extended PHY Control Register #4,” GMII/MII ...
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TBI Mode Transmit Timing The following specifications are valid when the I/O power supply (VDDIOMAC) is 2.5V or 3.3V, ±5%, per the RGMII v2.0 specification, and the MAC/Media Interface Mode Select bits (see Register #4,” page 129) have been ...
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TBI Mode Receive Timing The following specifications are valid when the I/O power supply (VDDIOMAC) is 2.5V or 3.3V, ±5%, per the RGMII v2.0 specification, and the MAC/Media Interface Mode Select bits (see Register #4,” page 129) have been ...
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RGMII/RTBI Mode Timing For RGMII/RTBI modes, the following specifications are valid when the I/O power supply (VDDIOMAC) is 2.5V or 3.3V, ±5%, per the RGMII v2.0 specification, and the MAC/Media Interface Mode Select bits (see Extended PHY Control Register ...
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TXC (at transmitter) TX[8:5][3:0] TD[7:4][3:0] TX[9]TX[4] TXCTL TXC (at receiver) RXC (at transmitter) RX[8:5][3:0] RD[7:4][3:0] RX[9]RX[4] RXCTL RXC (at receiver) Figure 43. RGMII/RTBI Uncompensated AC Timing and Multiplexing The RGMII specification (v2.0) defines the relationship shown above between the clock ...
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In this operating mode, the VSC8211 expects the following relationship between TXCLK and TD on the transmit side and RXCLK and RD on the receive side (assuming internal delay on the transmit side and receive side internal delay set to ...
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JTAG Timing The following specifications are valid only when the I/O power supply (VDDIOCTRL either 3.3V, ±5%, or 2.5V, ±5%. Symbol Min T 100 TCK-Period T 45 TCK-High T 45 TCK-Low T 10 TDI/TMS-Setup T 10 TDI/TMS-Hold ...
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SMI Timing The following specifications are valid only when the I/O power supply (VDDIOMICRO either 3.3V, ±5%, or 2.5V, ±5%. Symbol Min F 0 MDC T 20 MDC-High T 20 MDC-Low T 10 MDIO-Setup T 10 MDIO-Hold ...
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MDINT Timing The following specifications are valid only when the I/O power supply (VDDIOMICRO either 3.3V, ±5%, or 2.5V, ±5%. Symbol Min t F 30.11 Serial LED_CLK and LED_DATA Timing The following specifications are valid only when ...
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REFCLK Timing The following specifications are valid only when the VDD33A is at 3.3V, ±5%. For more information about clocking and frequency offset tolerance specifications when jumbo packet support is required, see the application note Using Jumbo Packets with ...
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CLKOUTMAC and CLKOUTMICRO Timing The following specifications are valid only when the I/O power supply (VDDIOMAC for CLKOUTMAC and VDDIOMICRO for CLKOUTMICRO either 3.3V ±5%, or 2.5V ±5%. . Table 72. CLKOUTMAC and CLKOUTMICRO Timing Symbol Min ...
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Reset Timing The following specifications are valid only when the I/O power supply (VDDIOctrl either 3.3 V, ±5%, or 2.5 V, ±5%. Symbol Min Typ T 100 RESET T 13 READY REFCLK RESET MDIO VMDS-10105 Revision 4.1 ...
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Packaging Specifications Figure 52. 117-ball 10x14mm LBGA Mechanical Specification 31.1 Package Moisture Sensitivity Moisture sensitivity level ratings for Vitesse products comply with the joint IPC and JEDEC standard IPC/JEDEC J-STD-020. All Vitesse products are rated moisture sensitivity level 3 ...
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... Package Type 1 1.0mm ball pitch VSC8211VW 10mm x 14mm body VSC8211XVW 1.0mm ball pitch 10mm x 14mm body 1 This device was previously available from Cicada Semiconductor Corporation (Cicada) as CIS8211-BLC. Cicada is now wholly owned by Vitesse Semiconductor Corporation, and the part number has been changed to reflect this. ...
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Design Guidelines These guidelines apply to Revision C of the VSC8211 silicon. 33.1 Required PHY Register Write Sequence At initialization, a number of internal registers must be changed from their default values. A series of register writes must be ...
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Initialization Script The 100BASE-FX initialization script does the following: • Initializes the copper section of DSP to support the 100BASE-FX mode • Disables the pair swap option • Sets 100BASE-X PCS into FX mode • Forces the PHY ...
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phy_write(0, 31, 0x52b5); phy_write(0, 0, 0xa25c); phy_write(0, 2, 0x0000); phy_write(0, 1, 0x3000); phy_write(0, 0, 0x825c); phy_write(0, 31, 0x52b5); phy_write(0, 0, 0xa25c); phy_write(0, 2, 0x0000); phy_write(0, 1, 0x3000); phy_write(0, 0, 0x825c); phy_write(0, 31, 0x52b5); phy_write(0, 0, 0xa25e); phy_write(0, 2, 0x0000); phy_write(0, ...
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VMDS-10105 Revision 4.1 October 2006 164 of 165 VSC8211 Datasheet ...
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... Vitesse, ASIC-Friendly, FibreTimer, TimeStream, Snoop Loop, Super FEC, FOCUSConnect, Meigs-II, Meigs-IIe, Lansing, Campbell-I, Barrington, PaceMaker, HOVCAT48, HOVCAT48e, HOVCAT192, HOVCAT192e, Micro PHY, FOCUS32, FOCUS16, IQ2200, OctalMAC, EQ Technology are trademarks or registered trademarks in the United States and/or other jurisdictions of Vitesse Semiconductor Corporation. All other trademarks or registered trademarks mentioned herein are the property of their respective holders. ...