PIC16F684-E/P Microchip Technology Inc., PIC16F684-E/P Datasheet - Page 69

• Manufacturer Part Number: PIC16F684-E/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F684-E/P

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 9-2:
9.1.5
The ADC module allows for the ability to generate an
interrupt upon completion of an analog-to-digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
interrupt service routine.
Please see Section 9.1.5 “Interrupts” for more
information.
FIGURE 9-3:
© 2006 Microchip Technology Inc.
Note:
(ADFM = 0)
(ADFM = 1)
INTERRUPTS
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
T
CY
Set GO/DONE bit
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
to T
AD
Conversion Starts
ANALOG-TO-DIGITAL CONVERSION T
10-BIT A/D CONVERSION RESULT FORMAT
MSB
bit 7
bit 7
T
AD
Unimplemented: Read as ‘0’
1 T
AD
b9
2 T
AD
b8
ADRESH
3 T
10-bit A/D Result
AD
b7
4 T
AD
b6
5 T
MSB
AD
b5
6 T
bit 0
bit 0
9.1.6
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 9-4 shows the two output formats.
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
AD
b4
7 T
AD
AD
b3
bit 7
bit 7
CYCLES
8 T
RESULT FORMATTING
10-bit A/D Result
LSB
AD
b2
9
T
AD
b1
Unimplemented: Read as ‘0’
10 T
ADRESL
PIC16F684
AD
b0
11
DS41202D-page 67
bit 0
LSB
bit 0