PIC18F2450-I/ML Microchip Technology Inc., PIC18F2450-I/ML Datasheet - Page 183
PIC18F2450-I/ML
Manufacturer Part Number
PIC18F2450-I/ML
Description
Microcontroller; 16 KB Flash; 768 RAM; 0 EEPROM; 23 I/O; 28-Pin-QFN
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2450-IML.pdf
(320 pages)
Specifications of PIC18F2450-I/ML
A/d Inputs
10-Channel, 10-Bit
Cpu Speed
12 MIPS
Eeprom Memory
0 Bytes
Input Output
23
Interface
EUSART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin QFN
Programmable Memory
16K Bytes
Ram Size
768 Bytes
Speed
48 MHz
Timers
1-8-bit, 2-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2450-I/ML
Manufacturer:
TOSHIBA
Quantity:
2 000
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16.6
Figure 16-4 shows the operation of the A/D converter
after the GO/DONE bit has been set and the
ACQT2:ACQT0 bits are cleared. A conversion is
started after the following instruction to allow entry into
Sleep mode before the conversion begins.
Figure 16-5 shows the operation of the A/D converter
after
ACQT2:ACQT0 bits are set to ‘010’ and selecting a
4 T
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will NOT be updated with the partially completed
A/D
ADRESH:ADRESL registers will continue to contain
the value of the last completed conversion (or the last
value written to the ADRESH:ADRESL registers).
FIGURE 16-4:
FIGURE 16-5:
© 2006 Microchip Technology Inc.
(Holding capacitor continues
acquiring input)
Set GO/DONE bit
AD
1
acquisition time before the conversion starts.
the
T
conversion
Set GO/DONE bit
CY
A/D Conversions
Holding capacitor is disconnected from analog input (typically 100 ns)
T
ACQ
Acquisition
- T
Automatic
2
GO/DONE
Time
AD
Conversion starts
Cycles
T
AD
3
1 T
sample.
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
bit
2 T
Conversion starts
(Holding capacitor is disconnected)
has
AD
b8
1
This
3 T
been
AD
b9
b7
2
means
4 T
Advance Information
set,
AD
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
b8
3
b6
AD
AD
5 T
On the following cycle:
ADRESH:ADRESL is loaded, GO/DONE bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (ACQT<2:0> = 000, T
CYCLES (ACQT<2:0> = 010, T
the
the
AD
b5
b7
4
6 T
AD
T
b4
5
b6
AD
7 T
Cycles
After the A/D conversion is completed or aborted, a
2 T
started. After this wait, acquisition on the selected
channel is automatically started.
16.7
The discharge phase is used to initialize the value of
the capacitor array. The array is discharged before
every sample. This feature helps to optimize the unity-
gain amplifier as the circuit always needs to charge the
capacitor array, rather than charge/discharge based on
previous measurement values.
AD
Note:
b3
b5
6
AD
8
wait is required before the next acquisition can be
T
AD
b4
Discharge
b2
PIC18F2450/4450
7
9 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
AD
b3
b1
8
10
T
AD
b0
ACQ
b2
9
ACQ
11
= 0)
T
AD
= 4 T
10
Discharge
b1
1
AD
DS39760A-page 181
b0
11
)
T
Discharge
AD
1
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