PIC18F252-I/SO Microchip Technology Inc., PIC18F252-I/SO Datasheet - Page 224
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PIC18F252-I/SO
Manufacturer Part Number
PIC18F252-I/SO
Description
Microcontroller; 32 KB Flash; 1536 RAM; 256 EEPROM; 25 I/O; 28-Pin-SOIC
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F252-ISO.pdf
(332 pages)
Specifications of PIC18F252-I/SO
A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SOIC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F252-I/SO
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PIC18FXX2
BNOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39564C-page 222
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Overflow
If Overflow
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Overflow
[ label ] BNOV
-128
if overflow bit is ’0’
(PC) + 2 + 2n
None
If the Overflow bit is ’0’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
'n'
'n'
=
=
=
=
=
n
address (HERE)
0;
address (Jump)
1;
address (HERE+2)
127
0101
BNOV Jump
operation
Process
Process
Data
Data
No
Q3
Q3
PC
n
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
BNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If Zero
If Zero
No
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Zero
[ label ] BNZ
-128
if zero bit is ’0’
(PC) + 2 + 2n
None
If the Zero bit is ’0’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
Q2
'n'
'n'
=
=
=
=
=
© 2006 Microchip Technology Inc.
n
address (HERE)
0;
address (Jump)
1;
address (HERE+2)
127
0001
BNZ
operation
Process
Process
Data
Data
No
Q3
Q3
n
PC
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
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