PIC12F683-I/SN Microchip Technology Inc., PIC12F683-I/SN Datasheet

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PIC12F683-I/SN

Manufacturer Part Number
PIC12F683-I/SN
Description
8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC12F683-I/SN

A/d Inputs
4-Channel, 10-Bit
Comparators
1
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
5
Memory Type
Flash
Number Of Bits
8
Package Type
8-pin SOIC-N
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC12F683
Data Sheet
8-Pin Flash-Based, 8-Bit
CMOS Microcontrollers with
nanoWatt Technology
* 8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
© 2006 Microchip Technology Inc.
DS41211C

PIC12F683-I/SN Summary of contents

Page 1

... Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. © 2006 Microchip Technology Inc. PIC12F683 Data Sheet 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology DS41211C ...

Page 2

... Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs, K EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. L ® code hopping devices, Serial EE OQ © 2006 Microchip Technology Inc. ...

Page 3

... Flash/Data EEPROM Retention: > 40 years Program Memory Device Flash (words) SRAM (bytes) PIC12F683 2048 © 2006 Microchip Technology Inc. PIC12F683 nanoWatt Technology Low-Power Features: • Standby Current 2.0V, typical • Operating Current kHz, 2.0V, typical - 220 MHz, 2.0V, typical • Watchdog Timer Current ...

Page 4

... Only when pin is configured for external MCLR. DS41211C-page GP0/AN0/CIN+/ICSPDAT/ULPWU 3 GP1/AN1/CIN-/ GP2/AN2/T0CKI/INT/COUT/CCP1 PIC12F683 PIC12F683 Timer CCP Interrupts Pull-ups — — IOC — — IOC T0CKI CCP1 INT/IOC — — IOC — IOC T1G T1CKI — IOC — — — — /ICSPCLK ...

Page 5

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2006 Microchip Technology Inc. PIC12F683 DS41211C-page 3 ...

Page 6

... PIC12F683 NOTES: DS41211C-page 4 © 2006 Microchip Technology Inc. ...

Page 7

... DEVICE OVERVIEW The PIC12F683 is covered by this data sheet available in 8-pin PDIP, SOIC and DFN-S packages. Figure 2-1 shows a block diagram of the PIC12F683 device. Table 2-1 shows the pinout description. FIGURE 2-1: PIC12F683 BLOCK DIAGRAM Configuration Flash Program Memory Program 14 Bus ...

Page 8

... PIC12F683 TABLE 2-1: PIC12F683 PINOUT DESCRIPTION Name Function GP5/T1CKI/OSC1/CLKIN GP5 T1CKI OSC1 CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP4 AN3 T1G OSC2 CLKOUT GP3/MCLR/V GP3 PP MCLR V PP GP2/AN2/T0CKI/INT/COUT/CCP1 GP2 AN2 T0CKI INT COUT CCP1 GP1/AN1/CIN-/V /ICSPCLK GP1 REF AN1 CIN- V REF ICSPCLK GP0/AN0/CIN+/ICSPDAT/ULPWU GP0 ...

Page 9

... Program Memory Organization The PIC12F683 has a 13-bit program counter capable of addressing program memory space. Only the first (0000h-07FFh) for the PIC12F683 is physically implemented. Accessing a location above these boundaries will cause a wraparound within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 3-1) ...

Page 10

... PIC12F683 3.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 128 the PIC12F683. Each register is accessed, either directly or indirectly, through the File Select Register FSR (see Section 3.4 “Indirect Addressing, INDF and FSR Registers”). 3.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (see Table 3-1) ...

Page 11

... TABLE 3-1: PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 18, 90 01h TMR0 Timer0 Module Register 02h PCL Program Counter’s (PC) Least Significant Byte ...

Page 12

... PIC12F683 TABLE 3-2: PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 18, 90 81h OPTION_REG GPPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte ...

Page 13

... Status bits. For other instructions not affect- ing any Status bits, see the “Instruction Set Summary”. Note 1: Bits IRP and RP1 of the STATUS register are not used by the PIC12F683 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products ...

Page 14

... PIC12F683 3.2.2.2 OPTION Register The OPTION register is a readable and writable register, which contains various control bits to configure: • TMR0/WDT prescaler • External GP2/INT interrupt • TMR0 • Weak pull-ups on GPIO REGISTER 3-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 GPPU INTEDG ...

Page 15

... GIE of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0 R/W-0 R/W-0 INTE GPIE T0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) PIC12F683 R/W-0 R/W-0 INTF GPIF bit Bit is unknown DS41211C-page 13 ...

Page 16

... PIC12F683 3.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 3-4. REGISTER 3-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 EEIE ADIE CCP1IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ...

Page 17

... GIE of the INTCON register. User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. U-0 R/W-0 R/W-0 — CMIF OSFIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC12F683 R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown DS41211C-page 15 ...

Page 18

... PIC12F683 3.2.2.6 PCON Register The Power Control (PCON) register contains flag bits (see Table 12-2) to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOR ...

Page 19

... Application Note AN556, “Implementing a Table Read” (DS00556). 3.3.2 STACK The PIC12F683 family has an 8-level x 13-bit wide hardware stack (see Figure 3-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...

Page 20

... PIC12F683 FIGURE 3-4: DIRECT/INDIRECT ADDRESSING PIC12F683 Direct Addressing (1) From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figure 3-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. ...

Page 21

... INTOSC 4 MHz 110 2 MHz 101 1 MHz 100 500 kHz 011 250 kHz 010 125 kHz 001 31 kHz 000 Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM) PIC12F683 /4 output OSC is a calibrated FOSC<2:0> SCS<0> System Clock (CPU and Peripherals) DS41211C-page 19 ...

Page 22

... PIC12F683 3.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 3-1) controls the system clock and frequency selection options. The OSCCON register contains the following bits: • Frequency selection bits (IRCF) • Frequency Status bits (HTS, LTS) • System clock control bits (OSTS, SCS) ...

Page 23

... MHz 125 kHz to 8 MHz FIGURE 3-2: Clock from Ext. System Note 1: Alternate pin functions are listed in the Device Overview. MCU design is PIC12F683 Oscillator Delay Oscillator Warm-Up Delay (T ) WARM 2 instruction cycles 1 cycle of each 1024 Clock Cycles (OST (approx.) EXTERNAL CLOCK (EC) ...

Page 24

... PIC12F683 3.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 3-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier ...

Page 25

... System Clock Source (SCS) bit of the OSCCON register to ‘1’ or enable Two-Speed Start-up by setting the IESO bit in the Configuration Word register (CONFIG) to ‘1’. The HF Internal Oscillator (HTS) bit of the OSCCON register indicates whether the HFINTOSC is stable or not. PIC12F683 (High-Frequency Internal (Low-Frequency Internal See Section 12.0 “ ...

Page 26

... PIC12F683 3.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 3-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 ...

Page 27

... OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2006 Microchip Technology Inc. PIC12F683 3.5.5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFINTOSC, the new oscillator may already be shut down to save power (see Figure 3-6) ...

Page 28

... PIC12F683 FIGURE 3-6: INTERNAL OSCILLATOR SWITCH TIMING ( HFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC LFINTOSC IRCF <2:0> 0 System Clock Note 1: When going from LF to HF. HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC LFINTOSC IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time 2-cycle Sync HFINTOSC IRCF < ...

Page 29

... OSTS bit of the OSCCON register to remain clear. © 2006 Microchip Technology Inc. PIC12F683 When the Oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.4.1 “Oscillator Start-up Timer (OST)”). The OST will suspend program execution until 1024 oscillations are counted ...

Page 30

... PIC12F683 3.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 3-7: TWO-SPEED START-UP ...

Page 31

... Fail-Safe circuit is not active Clock during oscillator start-up (i.e., after exiting Failure Detected Reset or Sleep). After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify the oscillator start-up and that the system clock completed. PIC12F683 switchover has successfully DS41211C-page 29 ...

Page 32

... PIC12F683 FIGURE 3-9: FSCM TIMING DIAGRAM Sample Clock System Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES ...

Page 33

... CLRF ANSEL MOVLW 0Ch MOVWF TRISIO R/W-0 R-x R/W-0 GP4 GP3 GP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC12F683 ; ;Init GPIO ;Set GP<2:0> to ;digital I/O ; ;digital I/O ;Set GP<3:2> as inputs ;and set GP<5:4,1:0> ;as outputs R/W-0 R/W-0 GP1 GP0 ...

Page 34

... TRISIO<5> always reads ‘1’ and RCIO and EC modes. 4.2 Additional Pin Functions Every GPIO pin on the PIC12F683 has interrupt-on-change option and a weak pull-up option. GP0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 4.2.1 ANSEL REGISTER The ANSEL register is used to configure the Input mode of an I/O pin to analog ...

Page 35

... The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. © 2006 Microchip Technology Inc. R/W-0 R/W-1 R/W-1 ADCS0 ANS3 ANS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) . PIC12F683 R/W-1 R/W-1 ANS1 ANS0 bit Bit is unknown DS41211C-page 33 ...

Page 36

... PIC12F683 REGISTER 4-4: WPU: WEAK PULL-UP REGISTER U-0 U-0 R/W-1 — — WPU5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 WPU<5:4>: Weak Pull-up Control bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3 Unimplemented: Read as ‘ ...

Page 37

... BANKSEL PCON BSF PCON,ULPWUE ;Enable ULP Wake-up and BSF IOCA,0 BSF TRISA,0 MOVLW B’10001000’ ;Enable interrupt MOVWF INTCON SLEEP NOP PIC12F683 Wake-up Module” ; ;Turn off ;comparators ; ;RA0 to digital I/O ;Output high to ; ;charge capacitor ; ; ;Select RA0 IOC ;RA0 to input ; and clear flag ...

Page 38

... PIC12F683 4.2.5 PIN DESCRIPTIONS AND DIAGRAMS Each GPIO pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the comparator or the ADC, refer to the appropriate section in this data sheet. ...

Page 39

... WR CK GPIO TRISIO RD TRISIO RD GPIO IOC RD IOC Interrupt-on- change To Timer0 To INT To A/D Converter Note 1: Comparator mode and ANSEL determines Analog Input mode. PIC12F683 BLOCK DIAGRAM OF GP2 Analog Input Mode Weak GPPU Analog COUT Input Enable Mode COUT 1 0 I/O pin Analog ...

Page 40

... PIC12F683 4.2.5.4 GP3/MCLR/V PP Figure 4-4 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset with weak pull-up FIGURE 4-4: BLOCK DIAGRAM OF GP3 MCLRE Data Bus MCLRE Reset TRISIO ...

Page 41

... IOC2 IOC1 T0SE PSA PS2 PS1 GP4 GP3 GP2 GP1 T1SYNC TMR1CS TMR1ON TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 WPU4 — WPU2 WPU1 PIC12F683 BLOCK DIAGRAM OF GP5 INTOSC Mode (1) TMR1LPEN V DD Weak GPPU Oscillator Circuit OSC2 V DD I/O pin V SS INTOSC Mode (1) Q ...

Page 42

... PIC12F683 NOTES: DS41211C-page 40 © 2006 Microchip Technology Inc. ...

Page 43

... The incrementing edge is determined by the T0SE bit of the OPTION register. Counter mode is selected by setting the T0CS bit of the OPTION register to ‘1’. 8-bit Prescaler PSA 8 PS<2:0> 16-bit 16 PSA WDTPS<3:0> PIC12F683 Data Bus 8 1 Sync TMR0 2 Tcy 0 Set Flag bit T0IF on Overflow 1 WDT ...

Page 44

... PIC12F683 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the OPTION register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. ...

Page 45

... Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE GPIE T0IF INTF T0SE PSA PS2 PS1 PIC12F683 R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown Value on Value on Bit 0 all other POR, BOR Resets xxxx xxxx uuuu uuuu GPIF 0000 0000 ...

Page 46

... PIC12F683 6.0 TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • 16-bit timer/counter register pair (TMR1H:TMR1L) • Programmable internal or external clock source • 3-bit prescaler • Optional LP oscillator • Synchronous or asynchronous operation • Timer1 gate (count enable) via comparator or T1G pin • ...

Page 47

... The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. © 2006 Microchip Technology Inc. PIC12F683 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks ...

Page 48

... PIC12F683 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • ...

Page 49

... TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1 register Timer1 gate source. © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) /4) PIC12F683 R/W-0 R/W-0 TMR1CS TMR1ON bit Bit is unknown DS41211C-page 47 ...

Page 50

... PIC12F683 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 (1) CONFIG CPD CP MCLRE CMCON1 — — — INTCON GIE PEIE T0IE PIE1 EEIE ADIE CCP1IE PIR1 EEIF ADIF CCP1IF TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register ...

Page 51

... A write to T2CON occurs. • Any device Reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset). Note: TMR2 is not cleared when T2CON is written. TMR2 Output Reset TMR2 Postscaler Comparator 1 PR2 TOUTPS<3:0> PIC12F683 Sets Flag bit TMR2IF DS41211C-page 49 ...

Page 52

... PIC12F683 REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler ...

Page 53

... The black areas of the output of the comparator represents the uncertainty due to input offsets and response time less IN CMSYNC Timer1 (1) clock source CMCON0 D Q Q3*RD CMCON0 EN CL Reset OSC PIC12F683 SINGLE COMPARATOR + Output – To Timer1 Gate To COUT pin To Data Bus Set CMIF bit ). DS41211C-page 51 ...

Page 54

... PIC12F683 8.2 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 8-3. Since the analog input pins share their con- nection with a digital input, they have reverse biased ESD protection diodes to V and V DD input, therefore, must be between V SS input voltage deviates from this range by more than 0 ...

Page 55

... CIN+ I/O COUT (pin) Comparator Off (Lowest power) CM<2:0> = 111 I/O CIN- COUT I/O CIN+ COUT (pin) I/O Module CIS = Comparator Input Switch (CMCON0<3> Comparator Digital Output PIC12F683 COUT From CV Module REF CIS = 0 CIS = 1 COUT From CV Module REF CIS = 0 CIS = 1 COUT ...

Page 56

... PIC12F683 8.4 Comparator Control The CMCON0 register (Register 8-1) provides access to the following comparator features: • Mode selection • Output state • Output polarity • Input switch 8.4.1 COMPARATOR OUTPUT STATE The Comparator state can always be read internally via the COUT bit of the CMCON0 register. The comparator ...

Page 57

... Allow about 1 s for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. PIC12F683 COMPARATOR INTERRUPT TIMING W/O CMCON0 READ reset by software COMPARATOR INTERRUPT TIMING WITH ...

Page 58

... PIC12F683 8.7 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 15.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. The comparator is turned off by selecting mode CM< ...

Page 59

... See the Comparator Block Diagram (Figure 8- 2) and the Timer1 Block Diagram (Figure 6-1) for more information. U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) PIC12F683 R/W-1 R/W-0 T1GSS CMSYNC bit Bit is unknown DS41211C-page 57 ...

Page 60

... PIC12F683 8.11 Comparator Voltage Reference The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators. The following features are available: • Independent from Comparator operation • Two 16-level voltage ranges • Output clamped • Ratiometric with V DD The VRCON register (Register 8-3) controls the Voltage Reference module shown in Figure 8-7 ...

Page 61

... CMIE OSFIE TMR2IE TMR1IE — CMIF OSFIF TMR2IF GP4 GP3 GP2 GP1 TRISIO0 — VR3 VR2 VR1 PIC12F683 VRR 8R REF Value on Value on Bit 0 all other POR, BOR Resets ANS0 -000 1111 -000 1111 CM0 -0-0 0000 -0-0 0000 ---- --10 ---- --10 GPIF ...

Page 62

... PIC12F683 NOTES: DS41211C-page 60 © 2006 Microchip Technology Inc. ...

Page 63

... The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 9.2 “ADC Operation” for more information. PIC12F683 Left Justify 1 = Right Justify 10 ADRESH ADRESL ...

Page 64

... PIC12F683 ADC V 9.1.3 OLTAGE REFERENCE The VCFG bit of the ADCON0 register provides control of the positive voltage reference. The positive voltage reference can be either external voltage DD source. The negative voltage reference is always connected to the ground reference. 9.1.4 CONVERSION CLOCK The source of the conversion clock is software select- able via the ADCS bits of the ANSEL register ...

Page 65

... Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. PIC12F683 ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 delay is required before another acqui- DS41211C-page 63 ...

Page 66

... PIC12F683 9.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option. When the F clock source is selected, the RC ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion ...

Page 67

... ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current © 2006 Microchip Technology Inc. U-0 R/W-0 R/W-0 — CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC12F683 R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown DS41211C-page 65 ...

Page 68

... PIC12F683 REGISTER 9-2: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 9-3: ...

Page 69

... A P PLIE D ⎝ ⎠ 2047 ln(1/2047 10k ln(0.0004885) 50°C- 25°C 0.05µ /° has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD PIC12F683 5. Temperature Coefficient charged to within 1/2 lsb CHOLD charge response to V CHOLD APPLIED DS41211C-page 67 ...

Page 70

... PIC12F683 FIGURE 9-4: ANALOG INPUT MODEL ANx Rs C PIN Legend Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to LEAKAGE various junctions R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance HOLD FIGURE 9-5: ADC TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh 004h ...

Page 71

... GPIE T0IF INTF — CMIE OSFIE TMR2IE — CMIF OSFIF TMR2IF GP4 GP3 GP2 GP1 TRISIO1 PIC12F683 Value on Value on Bit 0 all other POR, BOR Resets ADON 00-- 0000 0000 0000 ANS0 -000 1111 -000 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu ...

Page 72

... PIC12F683 NOTES: DS41211C-page 70 © 2006 Microchip Technology Inc. ...

Page 73

... EECON2 (not a physically implemented register) • EEDAT • EEADR EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. PIC12F683 has 256 bytes of data EEPROM with an address range from 0h to FFh. REGISTER 10-1: EEDAT: EEPROM DATA REGISTER R/W-0 ...

Page 74

... PIC12F683 10.1 EECON1 and EECON2 Registers EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non- implemented and read as ‘0’s. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software ...

Page 75

... EEPROM. The WREN bit is not cleared by hardware. © 2006 Microchip Technology Inc. PIC12F683 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. ...

Page 76

... PIC12F683 10.5 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) EEPROM write. ...

Page 77

... TABLE 11-1: CCP MODE – TIMER RESOURCES REQUIRED CCP Mode Capture Compare PWM R/W-0 R/W-0 R/W-0 DC1B0 CCP1M3 CCP1M2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared PIC12F683 Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 CCP1M1 CCP1M0 bit Bit is unknown DS41211C-page 75 ...

Page 78

... PIC12F683 11.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin CCP1. An event is defined as one of the following and is configured by the CCP1M<3:0> bits of the CCP1CON register: • Every falling edge • Every rising edge • Every 4th rising edge • ...

Page 79

... TMRxIF of the PIR1 register. 2: Removing changing the contents of the CCPR1H and CCPR1L register pair, between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. PIC12F683 the match condition by DS41211C-page 77 ...

Page 80

... PIC12F683 11.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCP1 pin. The duty cycle, period and resolution are determined by the following registers: • PR2 • T2CON • CCPR1L • CCP1CON In Pulse-Width Modulation (PWM) mode, the CCP module produces 10-bit resolution PWM output on the CCP1 pin ...

Page 81

... PIC12F683 PULSE WIDTH = CCPR1L:CCP1CON<5:4> T (TMR2 Prescale Value) OSC DUTY CYCLE RATIO CCPR1L:CCP1CON<5:4> = ---------------------------------------------------------------------- - 4 PR2 + bits of OSC PWM RESOLUTION log 4 PR2 ...

Page 82

... PIC12F683 11.3.4 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. ...

Page 83

... T0IF INTF — CMIE OSFIE TMR2IE — CMIF OSFIF TMR2IF TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 TRISIO4 TRISIO3 TRISIO2 TRISIO1 PIC12F683 Value on Value on Bit 0 all other POR, BOR Resets CCP1M0 --00 0000 --00 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx CMSYNC ---- --10 ---- --10 GPIF ...

Page 84

... PIC12F683 NOTES: DS41211C-page 82 © 2006 Microchip Technology Inc. ...

Page 85

... SPECIAL FEATURES OF THE CPU The PIC12F683 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • ...

Page 86

... PIC12F683 REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER — — — bit 15 CPD CP MCLRE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘1’ bit 11 FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled ...

Page 87

... Word is not erased when using the specified bulk erase sequence in the “PIC12F6XX/16F6XX Memory Programming Specification” (DS41244) and thus, does not require reprogramming. 12.3 Reset The PIC12F683 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation ...

Page 88

... For additional information, refer to the Application Note AN607, “Power-up Trouble Shooting” (DS00607). 12.3.2 MCLR PIC12F683 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...

Page 89

... Power-up Timer will be re-initialized. Once V rises above V BOR 64 ms Reset. 12.3.5 BOR CALIBRATION The PIC12F683 stores the BOR calibration values in fuses located in the Calibration Word register (2008h). The Calibration Word register is not erased when using the specified Word “PIC12F6XX/16F6XX Memory Programming Specifi- cation” ...

Page 90

... Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F683 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers ...

Page 91

... TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2006 Microchip Technology Inc. T PWRT T OST T PWRT T OST DD T PWRT T OST PIC12F683 ) DS41211C-page 89 ...

Page 92

... PIC12F683 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS Register Address Power-on Reset W — xxxx xxxx INDF 00h/80h xxxx xxxx TMR0 01h xxxx xxxx PCL 02h/82h 0000 0000 STATUS 03h/83h 0001 1xxx FSR 04h/84h xxxx xxxx GPIO 05h --x0 x000 PCLATH 0Ah/8Ah ---0 0000 INTCON ...

Page 93

... Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with the interrupt vector (0004h) after execution © 2006 Microchip Technology Inc. PIC12F683 Wake-up from Sleep MCLR Reset WDT Reset Wake-up from Sleep through ...

Page 94

... PIC12F683 12.4 Interrupts The PIC12F683 has multiple interrupt sources: • External Interrupt GP2/INT • Timer0 Overflow Interrupt • GPIO Change Interrupts • Comparator Interrupt • A/D Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt • ...

Page 95

... If a change on the I/O pin should occur when any GPIO operation is being executed, then the GPIF interrupt flag may not get set. Wake-up (If in Sleep mode) T0IF T0IE INTF INTE GPIF GPIE PEIE GIE PIC12F683 The interrupt can be Interrupt to CPU DS41211C-page 93 ...

Page 96

... PIC12F683 FIGURE 12-8: INT PIN INTERRUPT TIMING OSC1 (3) CLKOUT (4) INT pin (1) (5) INTF flag (INTCON reg.) GIE bit (INTCON reg.) INSTRUCTION FLOW PC PC Instruction Inst (PC) Fetched Instruction Inst (PC – 1) Executed Note 1: INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3 the same whether Inst (PC single cycle or a 2-cycle instruction ...

Page 97

... W and STATUS registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC12F683 (see Figure 3-2), temporary holding regis- ters, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, makes it easier to context save and restore. ...

Page 98

... WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits of the OPTION register have the same function as in previous versions of the PIC12F683 Section 5.0 “Timer0 Module” for more information. 0 From Timer0 Clock Source ...

Page 99

... Bit is cleared (1) Bit 4 Bit 3 Bit 2 Bit 1 WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 T0SE PSA PS2 PS1 PWRTE WDTE FOSC2 FOSC1 PIC12F683 R/W-0 R/W-0 WDTPS0 SWDTEN bit Bit is unknown Value on Value on Bit 0 all other POR, BOR Resets ---0 1000 PS0 1111 1111 ...

Page 100

... PIC12F683 12.7 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • WDT will be cleared but keeps running. • PD bit in the STATUS register is cleared. • TO bit is set. • Oscillator driver is turned off. • I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance) ...

Page 101

... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. © 2006 Microchip Technology Inc OST (2) T (3) Interrupt Latency Processor in Sleep Inst( Inst( Dummy Cycle not been PIC12F683 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) DS41211C-page 99 ...

Page 102

... A special debugging adapter allows the ICD device to be used in place of a PIC12F683 device. The debugging adapter is the only source of the ICD device. When the ICD pin on the PIC12F683 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2 ...

Page 103

... INSTRUCTION SET SUMMARY The PIC12F683 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...

Page 104

... PIC12F683 TABLE 13-2: PIC12F683 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW – Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ ...

Page 105

... Operands: Operation: Status Affected: Description: BSF Syntax: f,d Operands: Operation: Status Affected: Description: BTFSC Syntax: k Operands: Operation: Status Affected: Description: f,d PIC12F683 Bit Clear f [ label ] BCF f 127 (f<b>) 0 None Bit ‘b’ in register ‘f’ is cleared. Bit Set f [ label ] BSF f 127 ...

Page 106

... PIC12F683 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next ...

Page 107

... The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. © 2006 Microchip Technology Inc. PIC12F683 INCFSZ Increment f, Skip if 0 Syntax: [ label ] INCFSZ f,d ...

Page 108

... PIC12F683 MOVF Move f Syntax: [ label ] MOVF f,d Operands 127 d [0,1] Operation: (f) (dest) Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status destination is W register the destination is file register f itself useful to test a file register since status flag Z is affected ...

Page 109

... Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 © 2006 Microchip Technology Inc. PIC12F683 RETLW Return with literal in W Syntax: [ label ] RETLW k Operands 255 Operation: k (W); TOS PC Status Affected: ...

Page 110

... PIC12F683 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d Operands 127 d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. ...

Page 111

... Syntax: Operands: Operation: Status Affected: Description: f<3:0> f<3:0> XORWF Syntax: Operands: Operation: Status Affected: Description: PIC12F683 Exclusive OR literal with W [ label ] XORLW 255 (W) .XOR The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register. ...

Page 112

... PIC12F683 NOTES: DS41211C-page 110 © 2006 Microchip Technology Inc. ...

Page 113

... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. PIC12F683 14.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...

Page 114

... PIC12F683 14.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...

Page 115

... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2006 Microchip Technology Inc. PIC12F683 14.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...

Page 116

... PIC12F683 14.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PICmicro devices in DIP packages pins. ...

Page 117

... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. © 2006 Microchip Technology Inc. ........................................................................... -0. – ∑ DIS PIC12F683 + 0.3V ∑ {( ∑(V – DS41211C-page 115 ...

Page 118

... PIC12F683 FIGURE 15-1: PIC12F683 VOLTAGE-FREQUENCY GRAPH, -40°C T +125°C A 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 15-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V 125 2.0 2.5 DS41211C-page 116 8 10 Frequency (MHz) ± ...

Page 119

... DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001C D001D D002* V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 Rise Rate to ensure VDD DD internal Power-on Reset signal * These parameters are characterized but not tested ...

Page 120

... PIC12F683 15.2 DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. (1, 2) D010 Supply Current ( D011* D012 D013* D014 D015 D016* D017 D018 D019 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

Page 121

... DC Characteristics: PIC12F683-I (Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020 Power-down Base (2) Current D021 D022 D023 D024 D025* D026 D027 * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

Page 122

... PIC12F683 15.4 PIC12F683 DC Characteristics: Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature Param Device Characteristics No. D020E Power-down Base (2) Current ( D021E D022E D023E D024E D025E* D026E D027E * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...

Page 123

... Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. © 2006 Microchip Technology Inc. PIC12F683-I (Industrial) PIC12F683-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...

Page 124

... Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 “Using the Data EEPROM” for additional information. 5: Including OSC2 in CLKOUT mode. DS41211C-page 122 PIC12F683-I (Industrial) PIC12F683-E (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...

Page 125

... PDIP package 38.8 °C/W 8-pin SOIC package 3.0 °C/W 8-pin DFN-S 4x4x0.9 mm package 2.6 °C/W 8-pin DFN-S 6x5 mm package 150 °C For derated power calculations — — INTERNAL (NOTE 1) — — DER (NOTE DER PIC12F683 Conditions + P / INTERNAL DS41211C-page 123 ...

Page 126

... PIC12F683 15.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings Fall ...

Page 127

... AC Characteristics: PIC12F683 (Industrial, Extended) FIGURE 15-4: CLOCK TIMING Q4 OSC1/CLKIN OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C T Param Sym Characteristic No. OS01 F External CLKIN Frequency OSC (1) Oscillator Frequency ...

Page 128

... PIC12F683 TABLE 15-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. OS06 T Internal Oscillator Switch WARM (3) when running OS07 T Fail-Safe Sample Clock SC (1) Period OS08 HF Internal Calibrated OSC HFINTOSC Frequency OS09* LF Internal Uncalibrated OSC LFINTOSC Frequency ...

Page 129

... OS16 OS13 OS17 OS15 OS18, OS19 +125°C Min (1) — (1) — (1) — ( 200 ns OSC — 50 (Q2 cycle) 20 OSC (2) — — (2) — — PIC12F683 Execute Q3 OS12 OS18 OS14 New Value Typ† Max Units Conditions — 5.0V DD — 5.0V DD — — — ...

Page 130

... PIC12F683 FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out OSC Start-Up Time (1) Internal Reset Watchdog Timer (1) Reset I/O pins Note 1: Asserted low. FIGURE 15-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) ...

Page 131

... All specified values and V must be capacitively decoupled as close to the device PIC12F683 Conditions 5V, -40°C to +85° 5V, -40°C to +85° ...

Page 132

... PIC12F683 FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristic No. 40 T0CKI High Pulse Width T 41 T0CKI Low Pulse Width ...

Page 133

... Microchip Technology Inc. CC01 CC02 CC03 +125°C Min No Prescaler 0. With Prescaler 20 No Prescaler 0. With Prescaler PIC12F683 Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — prescale value ( 16) ...

Page 134

... PIC12F683 TABLE 15-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40° Param Sym Characteristics No. CM01 V Input Offset Voltage OS CM02 V Input Common Mode Voltage CM CM03* C Common Mode Rejection Ratio MRR CM04* T Response Time RT CM05 Comparator Mode Change Output Valid * These parameters are characterized but not tested ...

Page 135

... TABLE 15-9: PIC12F683 A/D CONVERTER (ADC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. AD01 N Resolution R AD02 E Integral Error IL AD03 E Differential Error DL AD04 E Offset Error OFF AD07 E Gain Error GN (3) AD06 V Reference Voltage REF AD06A AD07 ...

Page 136

... PIC12F683 TABLE 15-10: PIC12F683 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. AD130* T A/D Clock Period AD A/D Internal RC Oscillator Period AD131 T Conversion Time CNV (not including (1) Acquisition Time) AD132* T Acquisition Time ACQ AD133* T Amplifier Settling Time ...

Page 137

... FIGURE 15-10: PIC12F683 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO AD134 (T OSC Q4 A/D CLK A/D Data ADRES ADIF GO AD132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. FIGURE 15-11: PIC12F683 A/D CONVERSION TIMING (SLEEP MODE) ...

Page 138

... PIC12F683 NOTES: DS41211C-page 136 © 2006 Microchip Technology Inc. ...

Page 139

... MHz 2 MHz 4 MHz © 2006 Microchip Technology Inc. vs. F OVER V (EC MODE) OSC DD 6 MHz 8 MHz 10 MHz 12 MHz F OSC PIC12F683 5.5V 5.0V 4.0V 3.0V 2.0V 14 MHz 16 MHz 18 MHz 20 MHz DS41211C-page 137 DD ...

Page 140

... PIC12F683 FIGURE 16-2: MAXIMUM I DD 4.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp 3.5 (-40°C to 125°C) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz FIGURE 16-3: TYPICAL I DD 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp (-40° ...

Page 141

... Microchip Technology Inc. vs. F OVER V (HS MODE) OSC DD Maximum IDD vs. FOSC Over Vdd HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC vs. V OVER F (XT MODE) DD OSC XT Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD PIC12F683 5.5V 5.0V 4.5V 20 MHz 4.5 5.0 5.5 DS41211C-page 139 ...

Page 142

... PIC12F683 FIGURE 16-6: MAXIMUM I DD 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst-case Temp (-40°C to 125°C) 1,000 800 600 400 200 0 2.0 2.5 FIGURE 16-7: TYPICAL I DD 800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp 700 (-40°C to 125°C) ...

Page 143

... Microchip Technology Inc. vs. V (EXTRC MODE) DD EXTRC Mode 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD (LFINTOSC MODE, 31 kHz) OSC LFINTOSC Mode, 31KHZ Maximum Typical 3.0 3.5 4.0 V (V) DD PIC12F683 4.5 5.0 5.5 4.5 5.0 5.5 DS41211C-page 141 ...

Page 144

... PIC12F683 FIGURE 16-10: I vs. V (LP MODE Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40°C to 125° 2.0 2.5 FIGURE 16-11: TYPICAL I DD 1,600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp 1,400 (-40°C to 125°C) 1,200 1,000 800 600 400 ...

Page 145

... Microchip Technology Inc. vs. F OVER V (HFINTOSC MODE) OSC DD HFINTOSC 500 kHz 1 MHz 2 MHz F OSC vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED) DD Typical (Sleep Mode all Peripherals Disabled) 3.0 3.5 4.0 V (V) DD PIC12F683 5.5V 5.0V 4.0V 3.0V 2.0V 4 MHz 8 MHz 4.5 5.0 5.5 DS41211C-page 143 ...

Page 146

... PIC12F683 FIGURE 16-14: MAXIMUM I PD 18.0 Typical: Statistical Mean @25°C Maximum: Mean + 3 16.0 Maximum: Mean (Worst-case Temp (-40°C to 125°C) 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 2.0 2.5 FIGURE 16-15: COMPARATOR I 180 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp 140 (-40° ...

Page 147

... Microchip Technology Inc. OVER TEMPERATURE DD Maximum Typical 3.5 4.0 4.5 V (V) DD vs. V OVER TEMPERATURE PD DD Typical 3.0 3.5 4.0 V (V) DD PIC12F683 5.0 5.5 4.5 5.0 5.5 DS41211C-page 145 ...

Page 148

... PIC12F683 FIGURE 16-18: MAXIMUM WDT I 25.0 20.0 15.0 10.0 5.0 0.0 2.0 2.5 FIGURE 16-19: WDT PERIOD vs Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40°C to 125° 2.0 2.5 DS41211C-page 146 vs. V OVER TEMPERATURE PD DD Maximum Max. 125°C Maximum: Mean (Worst-case Temp (-40° ...

Page 149

... Microchip Technology Inc. (5.0V) DD Vdd = 5V Maximum Typical Minimum 25°C 85°C Temperature (°C) OVER TEMPERATURE (HIGH RANGE) DD High Range Max. 125°C Max. 85°C Typical 3.0 3.5 4.0 V (V) DD PIC12F683 125°C 4.5 5.0 5.5 DS41211C-page 147 ...

Page 150

... PIC12F683 FIGURE 16-22 vs. V REF PD 180 Typical: Statistical Mean @25°C 160 Maximum: Mean (Worst-case Temp (-40°C to 125°C) 140 120 100 2.0 2.5 FIGURE 16-23: V vs. I OVER TEMPERATURE ( 0.8 Typical: Statistical Mean @25°C 0.7 Maximum: Mean (Worst-case Temp (-40°C to 125°C) ...

Page 151

... Microchip Technology Inc. = 5.0V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 6.5 7.0 7.5 8.0 8.5 I (mA 3.0V) DD -1.5 -2.0 -2.5 I (mA) OH PIC12F683 9.0 9.5 10.0 Max. -40°C Typ. 25°C Min. 125°C -3.0 -3.5 -4.0 DS41211C-page 149 ...

Page 152

... PIC12F683 FIGURE 16-26: V vs. I OVER TEMPERATURE ( 5.5 5.0 4.5 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 FIGURE 16-27: TTL INPUT THRESHOLD V 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-case Temp (-40° ...

Page 153

... Input, -40×C TO 125×C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (32 kHz) DD Max. 125°C Max. 85°C Typ. 25°C 3.0 3.5 4.0 V (V) DD PIC12F683 OVER TEMPERATURE DD V Max. 125° Min. -40° Max. -40° Min. 125°C IL 4.5 5.0 5.5 4.5 5 ...

Page 154

... PIC12F683 FIGURE 16-30: COMPARATOR RESPONSE TIME (RISING EDGE) 531 806 1000 900 800 700 1.5V)/2 Note: 600 input = input = Transition from V 500 400 300 200 100 0 2.0 FIGURE 16-31: COMPARATOR RESPONSE TIME (FALLING EDGE) 1000 900 800 700 1.5V)/2 600 Note: ...

Page 155

... Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40°C to 125°C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40°C to 125°C) 3.0 3.5 4.0 4.5 V (V) DD PIC12F683 4.5 5.0 5.5 5.0 5.5 DS41211C-page 153 ...

Page 156

... PIC12F683 FIGURE 16-34: TYPICAL HFINTOSC START-UP TIMES vs 85°C 12 25°C 10 -40° 2.0 2.5 3.0 FIGURE 16-35: MAXIMUM HFINTOSC START-UP TIMES vs 85°C 25°C 10 -40° 2.0 2.5 3.0 DS41211C-page 154 OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40° ...

Page 157

... TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2006 Microchip Technology Inc. OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp (-40°C to 125°C) 3.5 4.0 V (V) DD 3.0 3.5 4.0 V (V) DD PIC12F683 4.5 5.0 5.5 (25°C) DD 4.5 5.0 5.5 DS41211C-page 155 ...

Page 158

... PIC12F683 FIGURE 16-38: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE 2.0 2.5 FIGURE 16-39: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 DS41211C-page 156 3.0 3.5 4.0 V (V) DD 3.0 3.5 4.0 V (V) DD (85°C) DD 4.5 5.0 5.5 (125°C) DD 4.5 5.0 5.5 © 2006 Microchip Technology Inc. ...

Page 159

... FIGURE 16-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2006 Microchip Technology Inc. 3.0 3.5 4.0 4.5 V (V) DD PIC12F683 (-40°C) DD 5.0 5.5 DS41211C-page 157 ...

Page 160

... PIC12F683 NOTES: DS41211C-page 158 © 2006 Microchip Technology Inc. ...

Page 161

... Standard PICmicro device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2006 Microchip Technology Inc. PIC12F683 Example 12F683 e 3 ...

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... PIC12F683 17.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width ...

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... L .019 .025 .030 .008 .009 .010 B .013 .017 .020 PIC12F683 A2 MILLIMETERS MIN NOM MAX 8 1.27 1.35 1.55 1.75 1.32 1.42 1.55 0.10 0.18 0.25 5.79 6.02 6.20 3.71 3.91 3.99 4.80 4.90 5.00 0.25 0.38 ...

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... PIC12F683 8-Lead Plastic Dual-Flat, No-Lead Package (MD) 4x4x0.9 mm Body (DFN) – Saw Singulated D PIN 1 INDEX AREA (NOTE 1) TOP VIEW A3 SIDE VIEW Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Length (Note 3) Exposed Pad Width Overall Width (Note 3) Exposed Pad Length ...

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... E2 .152 .158 .163 D .236 BSC D1 .226 BSC D2 .085 .091 .097 B .014 .016 .019 L .020 .024 .030 R .014 12° PIC12F683 PIN 1 INDEX E2 MILLIMETERS* MIN NOM MAX 8 1.27 BSC 0.85 1.00 0.65 0.80 0.00 0.01 0.05 0.20 REF. 4.92 BSC 4.67 BSC 3.85 4 ...

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... PIC12F683 NOTES: DS41211C-page 164 © 2006 Microchip Technology Inc. ...

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... Revisions throughout document. Incorporated Golden Chapters. © 2006 Microchip Technology Inc. PIC12F683 APPENDIX B: MIGRATING FROM OTHER PICmicro DEVICES This discusses some of the issues in migrating from other PICmicro devices to the PIC12F683 device. B.1 PIC16F676 to PIC12F683 TABLE B-1: FEATURE COMPARISON Feature PIC16F676 Max Operating 20 MHz ...

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... PIC12F683 NOTES: DS41211C-page 166 © 2006 Microchip Technology Inc. ...

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... GP1 Pin....................................................................... 37 GP2 Pin....................................................................... 37 GP3 Pin....................................................................... 38 GP4 Pin....................................................................... 38 GP5 Pin....................................................................... 39 In-Circuit Serial Programming Connections.............. 100 Interrupt Logic ............................................................. 93 MCLR Circuit............................................................... 86 On-Chip Reset Circuit ................................................. 85 PIC12F683.................................................................... 5 Resonator Operation................................................... 22 Timer1......................................................................... 44 © 2006 Microchip Technology Inc. Timer2 ........................................................................ 49 TMR0/WDT Prescaler ................................................ 41 Watchdog Timer (WDT).............................................. 96 Brown-out Reset (BOR)...................................................... 87 Associated .................................................................. 88 Calibration ...

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... Customer Notification Service........................................... 171 Customer Support ............................................................. 171 D Data EEPROM Memory Associated Registers .................................................. 74 Code Protection .................................................... 71, 74 Data Memory Organization ................................................... 7 Map of the PIC12F683 .................................................. 8 DC and AC Characteristics Graphs and Tables ................................................... 137 DC Characteristics Extended and Industrial ............................................ 121 Industrial and Extended ............................................ 117 Development Support ....................................................... 111 Device Overview ................................................................... 5 E EEADR Register ...

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... Power-up Timer (PWRT) .................................................... 86 Specifications ........................................................... 129 Precision Internal Oscillator Parameters .......................... 127 Prescaler Shared WDT/Timer0................................................... 42 Switching Prescaler Assignment ................................ 42 Program Memory Organization............................................. 7 Map and Stack for the PIC12F683 ............................... 7 Programming, Device Instructions.................................... 101 R Reader Response............................................................. 172 Read-Modify-Write Operations ......................................... 101 Registers ADCON0 (ADC Control 0) .......................................... 65 ADRESH (ADC Result High) with ADFM = 0) ............ 66 ADRESH (ADC Result High) with ADFM = 1) ...

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... PIC12F683 WDTCON (Watchdog Timer Control).......................... 97 WPU (Weak Pull-Up GPIO) ........................................ 34 Resets ................................................................................. 85 Brown-out Reset (BOR) .............................................. 85 MCLR Reset, Normal Operation ................................. 85 MCLR Reset, Sleep .................................................... 85 Power-on Reset (POR) ............................................... 85 WDT Reset, Normal Operation ................................... 85 WDT Reset, Sleep ...................................................... 85 Revision History ................................................................ 165 S Sleep Power-Down Mode ..................................................... 98 Wake-up...................................................................... 98 Wake-up Using Interrupts ........................................... 98 Software Simulator (MPLAB SIM)..................................... 112 Special Event Trigger ...

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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notifi- cation and follow the registration instructions. © 2006 Microchip Technology Inc. PIC12F683 CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...

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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC12F683 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...

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... Pattern: 3-digit Pattern Code for QTP (blank otherwise) © 2006 Microchip Technology Inc. XXX Examples: Pattern a) PIC12F683-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC12F683-I/SN = Industrial Temp., SOIC package, 20 MHz (2) (Extended) Note 1: 2: PIC12F683 . F = Standard Voltage Range LF = Wide Voltage Range tape and reel PLCC, and TQFP packages only ...

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... France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08- Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 02/16/06 © 2006 Microchip Technology Inc. ...

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