PIC12F683-I/SN Microchip Technology Inc., PIC12F683-I/SN Datasheet - Page 107

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PIC12F683-I/SN

Manufacturer Part Number
PIC12F683-I/SN
Description
8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC12F683-I/SN

A/d Inputs
4-Channel, 10-Bit
Comparators
1
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
5
Memory Type
Flash
Number Of Bits
8
Package Type
8-pin SOIC-N
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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PIC12F683-I/SN
0
DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Description:
INCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
© 2006 Microchip Technology Inc.
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0
d
(f) - 1
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, then a NOP is
executed instead, making it a
2-cycle instruction.
Unconditional Branch
[ label ]
0
k
PCLATH<4:3>
None
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
Increment f
[ label ]
0
d
(f) + 1
Z
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
f
k
f
[0,1]
[0,1]
PC<10:0>
127
127
2047
(destination);
GOTO k
(destination)
INCF f,d
PC<12:11>
INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Increment f, Skip if 0
[ label ]
0
d
(f) + 1
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOP is executed
instead, making it a 2-cycle
instruction.
Inclusive OR W with f
[ label ]
0
d
(W) .OR. (f)
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
skip if result = 0
Inclusive OR literal with W
[ label ]
0
(W) .OR. k
Z
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
f
[0,1]
f
[0,1]
k
127
127
PIC12F683
255
(destination),
INCFSZ f,d
IORWF
IORLW k
(W)
(destination)
DS41211C-page 105
f,d

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