PIC12F683-I/SN Microchip Technology Inc., PIC12F683-I/SN Datasheet - Page 45

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PIC12F683-I/SN

Manufacturer Part Number
PIC12F683-I/SN
Description
8 PIN, 3.5 KB FLASH, 128 RAM, 6 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC12F683-I/SN

A/d Inputs
4-Channel, 10-Bit
Comparators
1
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
5
Memory Type
Flash
Number Of Bits
8
Package Type
8-pin SOIC-N
Programmable Memory
3.5K Bytes
Ram Size
128 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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0
REGISTER 5-1:
TABLE 5-1:
© 2006 Microchip Technology Inc.
TMR0
INTCON
OPTION_REG
TRISIO
Legend:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
R/W-1
GPPU
Name
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0
module.
A dedicated 16-bit WDT postscaler is available. See Section 12.6 “Watchdog Timer (WDT)” for more
information.
GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual PORT latch values in WPU register
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (F
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Timer0 Module Register
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
GPPU
INTEDG
Bit 7
GIE
R/W-1
OPTION_REG: OPTION REGISTER
BIT VALUE
INTEDG
PEIE
Bit 6
000
001
010
011
100
101
110
111
W = Writable bit
‘1’ = Bit is set
R/W-1
T0CS
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111
T0CS
TIMER0 RATE WDT RATE
Bit 5
T0IE
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
T0SE
INTE
Bit 4
R/W-1
T0SE
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
OSC
GPIE
Bit 3
PSA
/4)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
PSA
Bit 2
T0IF
PS2
Bit 1
INTF
PS1
R/W-1
PS2
GPIF
Bit 0
PS0
x = Bit is unknown
PIC12F683
xxxx xxxx
0000 0000
1111 1111
POR, BOR
R/W-1
Value on
PS1
DS41211C-page 43
uuuu uuuu
0000 000x
1111 1111
--11 1111
Value on
all other
R/W-1
Resets
PS0
bit 0

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