PIC18F24J10-I/SS Microchip Technology Inc., PIC18F24J10-I/SS Datasheet - Page 259
PIC18F24J10-I/SS
Manufacturer Part Number
PIC18F24J10-I/SS
Description
Microcontroller; 16 KB Flash; 1024 RAM; 0 EEPROM; 21 I/O; 28-Pin-SSOP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F24J10-ISS.pdf
(359 pages)
Specifications of PIC18F24J10-I/SS
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SSOP
Programmable Memory
16K Bytes
Ram Size
1K Bytes
Speed
40 MHz
Timers
1-8-bit, 2-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F24J10-I/SS
Manufacturer:
MICROCHIP
Quantity:
1 667
Part Number:
PIC18F24J10-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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CLRF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
FLAG_REG
FLAG_REG
Q1
register ‘f’
Clear f
CLRF
0 ≤ f ≤ 255
a ∈ [0,1]
000h → f
1 → Z
Z
Clears the contents of the specified
register.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
CLRF
Read
0110
Q2
=
=
f {,a}
5Ah
00h
101a
FLAG_REG, 1
Process
Data
Q3
ffff
register ‘f’
Write
Q4
ffff
Preliminary
PIC18F45J10 FAMILY
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
WDT Counter
WDT Counter
WDT Postscaler
TO
PD
Q1
operation
Clear Watchdog Timer
CLRWDT
None
000h → WDT,
000h → WDT postscaler,
1 → TO,
1 → PD
TO, PD
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits, TO
and PD, are set.
1
1
CLRWDT
0000
Q2
No
=
=
=
=
=
0000
?
00h
0
1
1
Process
Data
Q3
DS39682B-page 257
0000
operation
Q4
No
0100
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