PIC32MX675F512H-80I/PT Microchip Technology Inc., PIC32MX675F512H-80I/PT Datasheet - Page 83
PIC32MX675F512H-80I/PT
Manufacturer Part Number
PIC32MX675F512H-80I/PT
Description
512KB Flash, 64KB RAM, 80 MHz, USB, ENET, 8 DMA
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC32MX795F512H-80IPT.pdf
(254 pages)
Specifications of PIC32MX675F512H-80I/PT
A/d Inputs
16-Channel, 10-Bit
Comparators
2
Eeprom Memory
0 Bytes
Input Output
53
Interface
CAN/I2C/SPI/UART/USB
Memory Type
Flash
Number Of Bits
32
Package Type
64-pin TQFP
Programmable Memory
512K Bytes
Ram Size
64K Bytes
Speed
80 MHz
Temperature Range
–40 to +85 °C
Timers
5-16-bit
Voltage, Range
2.3-3.6 V
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F512H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-17:
TABLE 4-18:
Legend:
Note
Legend:
Note
3000 DMACON
3010
3020 DMAADDR
3030 DCRCCON
3040 DCRCDATA
3050 DCRCXOR
1:
1:
DMASTAT
2:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
DMACH<3> bit is not available on PIC32MX534/564/664/764 devices.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
(1)
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
DMA GLOBAL REGISTER MAP
DMA CRC REGISTER MAP
31/15
31/15
ON
—
—
—
—
—
30/14
FRZ
30/14
—
—
—
—
—
29/13
29/13
—
—
—
—
—
BYTO<1:0>
SUSPEND DMABUSY
28/12
28/12
—
—
—
(1)
27/11
27/11
WBO
—
—
—
PLEN<4:0>
26/10
26/10
—
—
—
—
—
25/9
25/9
—
—
—
—
—
DMAADDR<31:0>
DCRCDATA<31:0>
DCRCXOR<31:0>
24/8
BITO
24/8
—
—
—
—
Bits
Bits
CRCEN
23/7
23/7
—
—
—
—
—
CRCAPP
22/6
22/6
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
CRCTYP
21/5
21/5
—
—
—
—
—
20/4
20/4
Section 12.1.1 “CLR, SET and INV Registers”
—
—
—
—
—
—
RDWR
19/3
19/3
—
—
—
—
—
18/2
18/2
—
—
—
—
DMACH<2:0>
CRCCH<2:0>
for more information.
17/1
17/1
—
—
—
—
(2)
for more
16/0
16/0
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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