PIC16F684-I/SL Microchip Technology Inc., PIC16F684-I/SL Datasheet - Page 12

• Manufacturer Part Number: PIC16F684-I/SL
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F684-I/SL

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin SOIC-N
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F684
TABLE 2-2:
DS41202D-page 10
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
Addr
1:
2:
3:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISC
PCLATH
INTCON
PIE1
PCON
OSCCON
OSCTUNE
ANSEL
PR2
WPUA
IOCA
VRCON
EEDAT
EEADR
EECON1
EECON2
ADRESL
ADCON1
Name
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
OSTS bit of the OSCCON register reset to ‘0’ with Dual Speed Start-up and LP, HS or XT selected as the oscillator.
RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
—
—
—
—
—
—
—
—
(3)
PIC16F684 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Module Period Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
EEPROM Control Register 2 (not a physical register)
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
EEADR7
EEDAT7
RAPU
VREN
IRP
ANS7
EEIE
Bit 7
GIE
—
—
—
—
—
—
—
—
—
—
(1)
EEADR6
EEDAT6
INTEDG
ADCS2
RP1
IRCF2
ANS6
PEIE
ADIE
Bit 6
—
—
—
—
—
—
—
—
—
(1)
ULPWUE
EEADR5
EEDAT5
CCP1IE
TRISA5
TRISC5
WPUA5
ADCS1
IOCA5
IRCF1
T0CS
ANS5
Bit 5
T0IE
VRR
RP0
—
—
—
SBOREN
EEADR4
EEDAT4
TRISA4
TRISC4
WPUA4
ADCS0
IOCA4
IRCF0
TUN4
ANS4
T0SE
INTE
C2IE
Bit 4
TO
—
—
Write Buffer for upper 5 bits of Program Counter
EEADR3
EEDAT3
WRERR
OSTS
TRISA3
TRISC3
IOCA3
TUN3
ANS3
RAIE
C1IE
Bit 3
PSA
VR3
PD
—
—
—
(2)
EEADR2
EEDAT2
TRISC2
WPUA2
TRISA2
WREN
OSFIE
IOCA2
TUN2
ANS2
Bit 2
T0IF
HTS
PS2
VR2
—
—
Z
EEADR1
TMR2IE
EEDAT1
TRISA1
TRISC1
WPUA1
IOCA1
TUN1
ANS1
Bit 1
INTF
POR
VR1
PS1
LTS
WR
DC
—
© 2006 Microchip Technology Inc.
EEADR0
EEDAT0
TMR1IE
TRISA0
TRISC0
WPUA0
IOCA0
TUN0
ANS0
RAIF
Bit 0
BOR
SCS
PS0
VR0
RD
—
C
xxxx xxxx 19, 104
1111 1111 14, 104
0000 0000 19, 104
0001 1xxx 13, 104
xxxx xxxx 19, 104
--11 1111 31, 104
--11 1111 40, 104
---0 0000 19, 104
0000 0000 15, 104
0000 0000 16, 104
--01 --qq 18, 104
-110 x000 20, 104
---0 0000 24, 105
1111 1111 32, 105
1111 1111 53, 105
--11 -111 33, 105
--00 0000 33, 105
0-0- 0000 63, 105
0000 0000 75, 105
0000 0000 75, 105
---- x000 76, 105
---- ---- 76, 105
xxxx xxxx 71, 105
-000 ---- 70, 105
POR, BOR
Value on
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