PIC16F684-I/SL Microchip Technology Inc., PIC16F684-I/SL Datasheet - Page 98

• Manufacturer Part Number: PIC16F684-I/SL
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F684-I/SL

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin SOIC-N
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F684
REGISTER 11-3:
TABLE 11-5:
DS41202D-page 96
CCPR1L
CCPR1H
CCP1CON
CMCON0
CMCON1
ECCPAS
INTCON
PIE1
PIR1
PR2
PWM1CON
T1CON
T2CON
TMR1L
TMR1H
TMR2
TRISA
TRISC
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture,
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-0
Note 1:
Name
PRSEN
R/W-0
Compare and PWM.
Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1
Timer2 Module Period Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module Register
T1GINV
C2OUT
PRSEN
P1M1
EEIE
EEIF
Bit 7
GIE
—
—
—
—
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
PDC<6:0>: PWM Delay Count bits
PDCn = Number of F
SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND PWM
R/W-0
PDC6
away; the PWM restarts automatically
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
PWM1CON: ENHANCED PWM CONTROL REGISTER
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
C1OUT
PDC6
P1M0
PEIE
ADIE
ADIF
Bit 6
should transition active and the actual time it transitions active
—
—
—
W = Writable bit
‘1’ = Bit is set
CCP1IE
CCP1IF
TRISC5
TRISA5
DC1B1
R/W-0
PDC5
C2INV
PDC5
Bit 5
T0IE
—
OSC
/4 (4 * T
TRISA4
TRISC4
DC1B0
C1INV
PDC4
INTE
Bit 4
C2IE
C2IF
—
R/W-0
PDC4
OSC
CCP1M3
TRISA3
TRISC3
) cycles between the scheduled time when a PWM signal
PDC3
RAIE
C1IE
Bit 3
C1IF
CIS
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
PDC3
CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
PSSAC0
TRISC2
TRISA2
OSFIE
OSFIF
PDC2
Bit 2
CM2
T0IF
—
PSSBD1
TMR2IE
TMR2IF
TRISA1
TRISC1
T1GSS
PDC1
INTF
Bit 1
CM1
R/W-0
PDC2
C2SYNC ---- --10 ---- --10
PSSBD0 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IF 0000 0000 0000 0000
TRISC0
TRISA0
PDC0
RAIF
Bit 0
CM0
© 2006 Microchip Technology Inc.
x = Bit is unknown
R/W-0
PDC1
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
--11 1111 --11 1111
--11 1111 --11 1111
POR, BOR
Value on:
R/W-0
PDC0
Value on
all other
Resets
bit 0