PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 106

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
11.2.2
The receiver block diagram is shown in Figure 11-4.
The data is received on the RB2/SDO/RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter, operating at x16 times
the baud rate; whereas, the main receive serial shifter
operates at the bit rate or at F
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the Receive (Serial) Shift
Register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit, RCIF (PIR1<5>), is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double-buffered register (i.e., it is a two-deep FIFO). It
FIGURE 11-4:
FIGURE 11-5:
DS30487C-page 104
Note:
RX pin
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
RB2/SDO/RX/DT
AUSART ASYNCHRONOUS
RECEIVER
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,
causing the OERR (Overrun) bit to be set.
F
OSC
Start
AUSART RECEIVE BLOCK DIAGRAM
ASYNCHRONOUS RECEPTION
bit
Baud Rate Generator
x64 Baud Rate CLK
bit 0
and Control
OSC
SPBRG
Pin Buffer
SPEN
bit 1
.
bit 7/8
Recovery
Stop
bit
Interrupt
Data
or
64
16
Word 1
RCREG
Start
CREN
bit
bit 0
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the Stop bit of the third byte, if the RCREG register is
still full, the Overrun Error bit, OERR (RCSTA<1>), will
be set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in soft-
ware. This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhib-
ited and no further data will be received. It is, therefore,
essential to clear error bit OERR if it is set. Framing
Error bit, FERR (RCSTA<2>), is set if a Stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values; therefore, it is essential for the user to read the
RCSTA register, before reading the RCREG register, in
order not to lose the old FERR and RX9D information.
RCIF
RCIE
RX9
MSb
Stop
bit 7/8
Word 2
RCREG
RX9D
(8) 7
OERR
Stop
bit
RCREG Register
RSR Register
Start
 2005 Microchip Technology Inc.
bit
8
Data Bus
1
FERR
0
bit 7/8
Start
FIFO
LSb
Stop
bit