PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 113

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 11-11:
11.4
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB5/SS/TX/CK pin (instead of being supplied inter-
nally in Master mode). This allows the device to trans-
fer or receive data while in Sleep mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
11.4.1
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
TABLE 11-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
 2005 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
19h
8Ch
98h
99h
Legend:
Note 1:
Address
RB2/SDO/RX/DT
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
RB5/SS/TX/CK
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
(Interrupt)
CREN bit
bit SREN
SREN bit
AUSART Synchronous Slave Mode
RCIF bit
RXREG
Write to
Read
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
AUSART SYNCHRONOUS SLAVE
TRANSMIT
INTCON
PIR1
RCSTA
TXREG
PIE1
TXSTA
SPBRG
pin
pin
Name
Q2
‘0’
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AUSART Transmit Data Register
Baud Rate Generator Register
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CSRC
SPEN
Bit 7
GIE
—
—
ADIF
ADIE
bit 0
PEIE
Bit 6
RX9
TX9
(1)
(1)
TMR0IE INT0IE
SREN
TXEN
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RCIF
RCIE
bit 1
Bit 5
CREN ADDEN
SYNC
TXIE
Bit 4
TXIF
bit 2
SSPIF
SSPIE
RBIE
Bit 3
bit 3
—
e)
When setting up a synchronous slave transmission,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
TMR0IF
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
BRGH
FERR
Bit 2
If enable bit TXIE is set, the interrupt will wake
the chip from Sleep and if the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
bit 4
INT0IF
OERR
TRMT
Bit 1
bit 5
RX9D
TX9D
PIC16F87/88
RBIF
Bit 0
bit 6
0000 000x 0000 000u
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
POR, BOR
Value on:
bit 7
DS30487C-page 111
Q1 Q2 Q3 Q4
Value on
all other
Resets
‘0’