PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 120

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
12.2
The A/D conversion time per bit is defined as T
A/D conversion requires 9.0 T
The source of the A/D conversion clock is software
selectable. The seven possible options for T
• 2 T
• 4 T
• 8 T
• 16 T
• 32 T
• 64 T
• Internal A/D module RC oscillator (2-6 s)
For correct A/D conversions, the A/D conversion clock
(T
as small as possible, but no less than 1.6 s and not
greater than 6.4 s.
Table 12-1 shows the resultant T
the device operating frequencies and the A/D clock
source selected.
TABLE 12-1:
DS30487C-page 118
Note 1:
AD
) must be selected to ensure a minimum T
OSC
OSC
OSC
OSC
OSC
OSC
2:
3:
Operation
RC
16 T
32 T
64 T
Selecting the A/D Conversion
Clock
2 T
4 T
8 T
The RC source has a typical T
When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for Sleep operation.
For extended voltage devices (LF), please refer to Section 18.0 “Electrical Characteristics”.
(1,2,3)
OSC
OSC
OSC
OSC
OSC
OSC
T
AD
vs. MAXIMUM DEVICE OPERATING FREQUENCIES – STANDARD DEVICES (C)
AD Clock Source (T
AD
AD
per 10-bit conversion.
ADCS<2>
times derived from
0
1
0
1
0
1
x
AD
AD
time of 4 s, but can vary between 2-6 s.
AD
AD
are:
. The
time
AD
)
ADCS<1:0>
12.3
The selection of the automatic acquisition time and
A/D conversion clock is determined in part by the clock
source and frequency while in a power-managed
mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON0 and ADCON1 should be updated in accor-
dance with the power-managed mode clock that will be
used. After the power-managed mode is entered
(either of the power-managed Run modes), an A/D
acquisition or conversion may be started. Once an
acquisition or conversion is started, the device should
continue to be clocked by the same power-managed
mode clock source until the conversion has been
completed.
If the power-managed mode clock frequency is less
than 1 MHz, the A/D RC clock source should be
selected.
00
00
01
01
10
10
11
Operation in Power-Managed
Modes
Maximum Device Frequency
 2005 Microchip Technology Inc.
1.25 MHz
2.5 MHz
(Note 1)
10 MHz
20 MHz
20 MHz
5 MHz
Max.