PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 146

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
15.12.4
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate even in the
event of an oscillator failure.
FIGURE 15-10:
The FSCM function is enabled by setting the FCMEN
bit in Configuration Word 2.
In the event of an oscillator failure, the FSCM will
generate an oscillator fail interrupt and will switch the
system clock over to the internal oscillator. The system
will continue to come from the internal oscillator until
the fail-safe condition is exited. The fail-safe condition
is exited with either a Reset, the execution of a SLEEP
instruction or a write to the OSCCON register.
The frequency of the internal oscillator will depend
upon the value contained in the IRCF bits. Another
clock source can be selected via the IRCF and the
SCS bits of the OSCCON register.
FIGURE 15-11:
DS30487C-page 144
31.25 kHz
Peripheral
Oscillator
(32 s)
INTRC
Clock
Note:
Sample Clock
CM Output
(488 Hz)
FAIL-SAFE OPTION
System
Output
OSFIF
Clock
(2.048 ms)
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
488 Hz
(Q)
÷ 64
FSCM BLOCK DIAGRAM
FSCM TIMING DIAGRAM
(edge-triggered)
Clock Monitor
Latch (CM)
C
S
Q
Q
CM Test
Detected
Failure
Clock
The FSCM sample clock is generated by dividing the
INTRC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur.
On the rising edge of the postscaled clock, the
monitoring latch (CM = 0) will be cleared. On a falling
edge of the primary or secondary system clock, the
monitoring latch will be set (CM = 1). In the event that
a falling edge of the postscaled clock occurs and the
monitoring latch is not set, a clock failure has been
detected.
While in Fail-Safe mode, a Reset will exit the fail-safe
condition. If the primary clock source is configured for
a crystal, the OST timer will wait for the 1024 clock
cycles for the OST time-out and the device will
continue running from the internal oscillator until the
OST is complete. A SLEEP instruction, or a write to the
SCS bits (where SCS bits do not = 00), can be
performed to put the device into a low-power mode.
If Reset occurs while in Fail-Safe mode and the pri-
mary clock source is EC or RC, then the device will
immediately switch back to EC or RC mode.
15.12.4.1
A write to the OSCCON register, or SLEEP instruction,
will end the fail-safe condition. The system clock will
default to the source selected by the SCS bits, which
is either T1OSC, INTRC or none (Sleep mode). How-
ever, the FSCM will continue to monitor the system
clock. If the secondary clock fails, the device will
immediately switch to the internal oscillator clock. If
OSFIE is set, an interrupt will be generated.
Note:
CM Test
Oscillator
Failure
Two-Speed Start-up mode is automatically
enabled when the fail-safe option is
enabled.
Fail-Safe in Low-Power Mode
 2005 Microchip Technology Inc.
Detected
Failure
CM Test