PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 16

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
2.2.2
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
DS30487C-page 14
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note 1:
Address
Bank 0
(2)
(2)
(2)
(2)
(1,2)
(2)
2:
3:
4:
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
ADRESH
ADCON0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
RA5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
PIC16F88 device only.
SPECIAL FUNCTION REGISTERS
Name
—
—
—
—
—
—
(4)
(4)
SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTA Data Latch when written; PORTA pins when read (PIC16F87)
PORTA Data Latch when written; PORTA pins when read (PIC16F88)
PORTB Data Latch when written; PORTB pins when read (PIC16F87)
PORTB Data Latch when written; PORTB pins when read (PIC16F88)
Unimplemented
Unimplemented
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module Register
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
AUSART Transmit Data Register
AUSART Receive Data Register
Unimplemented
Unimplemented
Unimplemented
A/D Result Register High Byte
ADCS1
WCOL
OSFIF
SPEN
Bit 7
IRP
GIE
—
—
—
—
—
TOUTPS3 TOUTPS2
T1RUN
SSPOV
ADCS0
ADIF
PEIE
CMIF
Bit 6
RP1
RX9
—
—
(4)
T1CKPS1
TMR0IE
SSPEN
CCP1X
SREN
CHS2
RCIF
Bit 5
RP0
—
—
Write Buffer for the Upper 5 bits of the Program Counter
TOUTPS1
T1CKPS0
CCP1Y
INT0IE
CREN
CHS1
Bit 4
TXIF
EEIF
CKP
TO
T1OSCEN
TOUTPS0
CCP1M3
ADDEN
SSPM3
SSPIF
CHS0
RBIE
Bit 3
PD
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
—
GO/DONE
TMR2ON
CCP1M2
T1SYNC
TMR0IF
CCP1IF
SSPM2
FERR
Bit 2
—
Z
T2CKPS1
TMR1CS
CCP1M1
TMR2IF
SSPM1
INT0IF
OERR
Bit 1
DC
—
—
 2005 Microchip Technology Inc.
T2CKPS0
TMR1ON
CCP1M0
TMR1IF
SSPM0
ADON
RX9D
RBIF
Bit 0
—
C
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx 0000
xxx0 0000
xxxx xxxx
00xx xxxx
---0 0000
0000 000x
-000 0000
00-0 ----
xxxx xxxx
xxxx xxxx
-000 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 00-0 114, 120
POR, BOR
Value on:
—
—
—
—
—
—
Details
26, 135
19, 69,
21, 77
23, 34
77, 83
77, 83
72, 83
80, 85
80, 85
90, 95
89, 95
83, 85
83, 85
81, 83
98, 99
page
135
135
103
105
120
on
69
17
52
58
77
—
—
—
—
—
—