PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 193

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 18-18:
TABLE 18-14: A/D CONVERSION REQUIREMENTS
 2005 Microchip Technology Inc.
130
131
132
134
Note 1:
Param
No.
A/D DATA
Note: If the A/D clock source is selected as RC, a time of T
SAMPLE
A/D CLK
2:
ADRES
T
T
T
T
*
†
§
Symbol
BSF ADCON0, GO
AD
CNV
ACQ
GO
ADIF
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
This specification ensured by design.
ADRES registers may be read on the following T
See Section 12.1 “A/D Acquisition Requirements” for minimum conditions.
GO
Q4
instruction to be executed.
A/D Clock Period
Conversion Time (not including S/H time)
(Note 1)
Acquisition Time
Q4 to A/D Clock Start
132
A/D CONVERSION TIMING
Characteristic
(T
OSC
/2)
9
(1)
PIC16F87/88
PIC16LF87/88
PIC16F87/88
PIC16LF87/88
8
OLD_DATA
7
CY
Sampling Stopped
(Note 2)
cycle.
Min
10*
1.6
3.0
2.0
3.0
—
CY
is added before the A/D clock starts. This allows the SLEEP
130
131
T
OSC
Typ†
4.0
6.0
40
—
—
—
—
/2 §
2
Max
6.0
9.0
12
—
—
—
—
—
1
Units
T
—
AD
s
s
s
s
s
s
PIC16F87/88
1 T
0
CY
T
T
A/D RC mode
A/D RC mode
The minimum time is the
amplifier settling time. This may
be used if the “new” input
voltage has not changed by
more than 1 LSb (i.e., 5.0 mV @
5.12V) from the last sampled
voltage (as stated on C
If the A/D clock source is
selected as RC, a time of T
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
OSC
OSC
based, V
based, V
NEW_DATA
DONE
Conditions
DS30487C-page 191
REF
REF
3.0V
2.0V
HOLD
CY
).
is