PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 70

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F87/88
6.3
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 T
a small RC delay of 20 ns) and low for at least 2 T
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
6.4
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
Timer0 module means that the prescaler cannot be
used by the Watchdog Timer and vice versa. This
prescaler is not readable or writable (see Figure 6-1).
REGISTER 6-1:
DS30487C-page 68
Using Timer0 with an External
Clock
Prescaler
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
OPTION_REG: OPTION CONTROL REGISTER (ADDRESS 81h, 181h)
bit 7
RBPU: PORTB Pull-up Enable bit
INTEDG: Interrupt Edge Select bit
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Legend:
R = Readable bit
-n = Value at POR
Bit Value TMR0 Rate WDT Rate
Note:
R/W-1
RBPU
000
001
010
011
100
101
110
111
To avoid an unintended device Reset, the instruction sequence shown in the
”PICmicro
executed when changing the prescaler assignment from Timer0 to the WDT. This
sequence must be followed even if the WDT is disabled.
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
INTEDG
R/W-1
®
OSC
Mid-Range MCU Family Reference Manual” (DS33023) must be
(and
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
OSC
R/W-1
W = Writable bit
‘1’ = Bit is set
T0CS
R/W-1
T0SE
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
Note:
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Although the prescaler can be assigned to
either the WDT or Timer0, but not both, a
new divide counter is implemented in the
WDT circuit to give multiple WDT time-out
selections. This allows TMR0 and WDT to
each have their own scaler. Refer to
Section 15.12 “Watchdog Timer (WDT)”
for further details.
Writing to TMR0, when the prescaler is
assigned
prescaler count but will not change the
prescaler assignment.
R/W-1
PSA
to
R/W-1
 2005 Microchip Technology Inc.
PS2
Timer0,
x = Bit is unknown
R/W-1
PS1
will
clear
R/W-1
PS0
bit 0
the