PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 75

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.2
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>), has no effect since the internal clock is
always in sync.
7.3
Timer1 may operate in Asynchronous or Synchronous
mode, depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
FIGURE 7-1:
FIGURE 7-2:
 2005 Microchip Technology Inc.
Note: Arrows indicate counter increments.
T1CKI
(Default High)
T1CKI
(Default Low)
Timer1 Operation in Timer Mode
Timer1 Counter Operation
OSC
T1OSO/T1CKI
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
/4. The synchronize control bit, T1SYNC
T1OSI
Set Flag bit
TMR1IF on
Overflow
TIMER1 INCREMENTING EDGE
TIMER1 BLOCK DIAGRAM
TMR1H
T1OSC
TMR1
TMR1L
T1OSCEN
Enable
Oscillator
(1)
Clock
Internal
F
OSC
TMR1ON
/4
On/Off
7.4
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RB7/PGD/T1OSI when bit
T1OSCEN is set, or on pin RB6/PGC/T1OSO/T1CKI
when bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synch-
ronization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during Sleep mode, Timer1 will not
increment even if the external clock is present since the
synchronization circuit is shut off. The prescaler,
however, will continue to increment.
TMR1CS
1
0
T1CKPS1:T1CKPS0
Timer1 Operation in Synchronized
Counter Mode
T1SYNC
Prescaler
1, 2, 4, 8
0
1
2
PIC16F87/88
Synchronized
Clock Input
Synchronize
Q Clock
det
DS30487C-page 73