PIC16F88-I/SO Microchip Technology Inc., PIC16F88-I/SO Datasheet - Page 85

• Manufacturer Part Number: PIC16F88-I/SO
• Description: 18 PIN, 7 KB FLASH, 368 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F88-I/SO

• A/d Inputs: 7-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 368 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
• Driven high
• Driven low
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit, CCP1IF, is set.
FIGURE 9-2:
TABLE 9-2:
 2005 Microchip Technology Inc.
0Bh,8Bh
10BH,18Bh
0Ch
8Ch
86h
0Eh
0Fh
10h
15h
16h
17h
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
Note 1:
CCP1 pin
Special Event Trigger will:
• Reset Timer1 but not set interrupt flag bit, TMR1IF
• Set bit GO/DONE (ADCON0<2>) which starts an A/D
Address
(PIR1<0>)
conversion
Output Enable
TRISB<x>
Compare Mode
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
INTCON
PIR1
PIE1
TRISB
TMR1L
TMR1H
T1CON
CCPR1L
CCPR1H
CCP1CON
Name
Q
Special Event Trigger
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
CCP1CON<3:0>
R
S
Mode Select
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
PORTB Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
Bit 7
GIE
—
—
—
—
(PIR1<2>)
Set Flag bit CCP1IF
ADIE
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
ADIF
PEIE
Bit 6
Match
—
(1)
(1)
CCPR1H CCPR1L
TMR1H
TMR0IE
CCP1X
Comparator
RCIE
RCIF
Bit 5
TMR1L
CCP1Y
INT0IE
TXIE
Bit 4
TXIF
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SSPIF
SSPIE
RBIE
Bit 3
9.2.1
The user must configure the CCP1 pin as an output by
clearing the TRISB<x> bit.
9.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
9.2.3
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
9.2.4
In this mode, an internal hardware trigger is generated
that may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1
register to effectively be a 16-bit programmable period
register for Timer1.
Note:
Note 1: Clearing the CCP1CON register will force
TMR0IF
CCP1IF TMR2IF
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
Bit 2
2: The TRISB bit (0 or 3) is dependent upon
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
the CCP1 compare output latch to the
default low level. This is not the data
latch.
the setting of configuration bit 12
(CCPMX).
INT0IF
Bit 1
PIC16F87/88
TMR1IF -000 0000 -000 0000
RBIF
Bit 0
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOR
Value on
DS30487C-page 83
Value on
all other
Resets