PIC16F887-I/PT Microchip Technology Inc., PIC16F887-I/PT Datasheet
PIC16F887-I/PT
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PIC16F887-I/PT Summary of contents
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... PIC16F882/883/884/886/887 28/40/44-Pin, Enhanced Flash-Based 8-Bit © 2007 Microchip Technology Inc. Data Sheet CMOS Microcontrollers with nanoWatt Technology Preliminary DS41291D ...
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... EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , K L logo, microID, MPLAB, PIC DSCs ® code hopping devices, Serial EE OQ © 2007 Microchip Technology Inc. ® ...
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... Operating Current μ kHz, 2.0V, typical - 220 μ MHz, 2.0V, typical • Watchdog Timer Current μA @ 2.0V, typical © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 nanoWatt Technology Peripheral Features: • 24/35 I/O pins with individual direction control: - High current source/sink for direct LED drive ...
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... PIC16F882/883/884/886/887 Program Data Memory Memory Device Flash SRAM (words) (bytes) PIC16F882 2048 128 PIC16F883 4096 256 PIC16F884 4096 256 PIC16F886 8192 368 PIC16F887 8192 368 DS41291D-page 2 10-bit A/D ECCP/ I/O (ch) CCP EEPROM (bytes) 128 28 11 1/1 256 24 11 1/1 256 35 14 ...
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... RC5 16 — — RC6 17 — — RC7 18 — — RE3 1 — — — 20 — — — 8 — — — 19 — — Note 1: Pull-up activated only with external MCLR configuration. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Timers ECCP EUSART MSSP — ...
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... PIC16F882/883/884/886/887 Pin Diagrams – PIC16F882/883/886, 28-Pin QFN 28-pin QFN RA2/AN2/V -/CV /C2IN+ REF REF RA3/AN3/V +/C1IN+ REF RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT V SS RA7/OSC1/CLKIN RA6/OSC2/CLKOUT DS41291D-page RB3/AN9/PGM/C12IN2 RB2/AN8/P1B 3 19 RB1/AN10/P1C/C12IN3- PIC16F882/883/886 4 18 RB0/AN12/INT RC7/RX/DT Preliminary DD SS © 2007 Microchip Technology Inc. ...
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... Note 1: Pull-up activated only with external MCLR configuration. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Timers ECCP EUSART MSSP — — — — — — — — — — — — ...
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... RC1/T1OSI/CCP2 RC2/P1A/CCP1 RC3/SCK/SCL RD0 RD1 DS41291D-page 6 40 RB7/ICSPDAT RB6/ICSPCLK 38 3 RB5/AN13/T1G 37 RB4/AN11 4 36 RB3/AN9/PGM/C12IN2 RB2/AN8 6 34 RB1/AN10/C12IN3 RB0/AN12/INT RD7/P1D 11 29 RD6/P1C 12 28 RD5/P1B 13 27 RD4 14 RC7/RX/ RC6/TX/ RC5/SDO 24 17 RC4/SDI/SDA 23 18 RD3 22 19 RD2 21 20 Preliminary © 2007 Microchip Technology Inc. ...
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... Note 1: Pull-up activated only with external MCLR configuration. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Timers ECCP EUSART MSSP — — — — — — — — — — — — ...
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... PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 44-Pin QFN 44-pin QFN RC7/RX/DT RD4 RD5/P1B RD6/P1C RD7/P1D RB0/AN12/INT RB1/AN10/C12IN3- RB2/AN8 DS41291D-page PIC16F884/887 Preliminary RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT © 2007 Microchip Technology Inc. ...
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... Note 1: Pull-up activated only with external MCLR configuration. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Timers ECCP EUSART MSSP — — — — — — — — — — — — ...
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... PIC16F882/883/884/886/887 Pin Diagrams – PIC16F884/887, 44-Pin TQFP 44-pin TQFP RC7/RX/DT RD4 RD5/P1B RD6/P1C RD7/P1D RB0/AN12/INT RB1/AN10/C12IN3- RB2/AN8 RB3/AN9/PGM/C12IN2- DS41291D-page PIC16F884/887 Preliminary NC RC0/T1OSO/T1CKI RA6/OSC2/CLKOUT RA7/OSC1/CLKIN RE2/AN7 RE1/AN6 RE0/AN5 RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT © 2007 Microchip Technology Inc. ...
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... Note 1: Pull-up activated only with external MCLR configuration. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Timers ECCP EUSART MSSP — — — — — — — — — — — — ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS41291D-page 12 Preliminary © 2007 Microchip Technology Inc. ...
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... PIC16F884/887 is available in a 40-pin PDIP and 44- pin QFN and TQFP packages. Figure 1-1 shows the block diagram of PIC16F882/883/886 and Figure 1-2 shows a block diagram of the PIC16F884/887 device. Table 1-1 and Table 1-2 show the corresponding pinout descriptions. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Preliminary DS41291D-page 13 ...
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... Indirect RB4 Addr RB5 RB6 RB7 PORTC RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 PORTE RE3 CCP2 CCP2 (ICD) Master Synchronous Serial Port (MSSP REF EEDATA REF CV (2) REF 128 / 256 Bytes Data EEPROM EEADDR © 2007 Microchip Technology Inc. ...
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... FIGURE 1-2: PIC16F884/PIC16F887 BLOCK DIAGRAM Configuration Flash ( Program Memory Program 14 Bus Instruction Reg Instruction Decode & Control OSC1/CLKIN Timing Generation OSC2/CLKOUT Internal Oscillator Block Timer1 T1OSI 32 kHz Oscillator T1OSO T1G T1CKI T0CKI Timer0 Timer1 V + Analog-To-Digital Converter REF (ADC REF Note 1: PIC16F884 only ...
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... Comparator negative input. TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN — A/D Channel 8. — CMOS PWM output. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Preliminary Description OD = Open Drain © 2007 Microchip Technology Inc. ...
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... Legend Analog input or output TTL = TTL compatible input HV = High Voltage © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN — A/D Channel 9. ST — Low-voltage ICSP™ Programming enable pin. ...
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... CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN — A/D Channel 9. ST — Low-voltage ICSP™ Programming enable pin. AN — Comparator negative input. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Preliminary Description OD = Open Drain © 2007 Microchip Technology Inc. ...
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... RD5/P1B RD5 P1B RD6/P1C RD6 P1C Legend Analog input or output TTL = TTL compatible input HV = High Voltage © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN — A/D Channel 11. ...
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... General purpose input. ST — Master Clear with internal pull-up. HV — Programming voltage. Power — Ground reference. Power — Positive supply. CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels XTAL = Crystal Preliminary Description OD = Open Drain © 2007 Microchip Technology Inc. ...
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... PIC16F882 (0000h-0FFFh) for the PIC16F883/PIC16F884, and (0000h-1FFFh) for the PIC16F886/PIC16F887 program memory space. Accessing a location above these boundaries will cause a wraparound within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 2-2 and 2-3) ...
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... GENERAL PURPOSE REGISTER FILE The register file is organized as 128 the PIC16F882, 256 the PIC16F883/PIC16F884, and 368 the PIC16F886/PIC16F887. Each register is accessed, either directly or indirectly, through the File Select Register (FSR) (see Section 2.4 “Indirect Addressing, INDF and FSR Registers”). Note: ...
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... Registers General 32 Bytes Purpose Registers 96 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 File File Address Address (1) (1) 80h Indirect addr. 100h 81h TMR0 101h 82h ...
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... Bank 3 © 2007 Microchip Technology Inc. ...
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... FIGURE 2-6: PIC16F886 PIC16F887 SPECIAL FUNCTION REGISTERS / File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC (2) PORTD 08h TRISD PORTE 09h TRISE ...
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... See Registers • and 13-4 for more detail. 3: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the data latches are either undefined (POR) or unchanged (other Resets). 4: PIC16F884/PIC16F887 only. DS41291D-page 26 Bit 5 Bit 4 Bit 3 ...
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... MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: Accessible only when SSPCON register bits SSPM<3:0> = 1001. 3: PIC16F884/PIC16F887 only. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Bit 5 Bit 4 ...
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... Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the mismatch exists. 2: PIC16F884/PIC16F887 only. DS41291D-page 28 Bit 5 Bit 4 Bit 3 Bit 2 ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘ ...
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... See Section 6.3 “Timer1 Prescaler”. R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) OSC WDT Rate 128 256 1 : 128 Preliminary R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clearing T0IF bit. 3: Includes ULPWU interrupt. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
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... DS41291D-page 32 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Disables Ultra Low-Power Wake-up interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables CCP2 interrupt 0 = Disables CCP2 interrupt © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 ...
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... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
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... Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register ...
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... Note 1: BOREN<1:0> the Configuration Word Register 1 for this bit to control the BOR. DS41291D-page 36 R/W-1 U-0 U-0 (1) SBOREN — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-x POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... PCLATH must be incremented for each address rollover that occurs between the table beginning and the target location within the table. For more information refer to Application Note AN556, “Implementing a Table Read” (DS00556). © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 2.3.2 STACK The PIC16F882/883/884/886/887 devices have an 8-level x 13-bit wide hardware stack (see Figures 2-2 and 2-3) ...
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... Location Select 00h Data Memory 7Fh Bank 0 Note: For memory map detail, see Figures 2-2 and 2-3. DS41291D-page 38 0 IRP Bank Select 180h Bank 1 Bank 2 Bank 3 Preliminary Indirect Addressing 7 0 File Select Register Location Select 1FFh © 2007 Microchip Technology Inc. ...
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... PORTA pin configured as an input (tri-stated PORTA pin configured as an output Note 1: TRISA<7:6> always reads ‘1’ in XT, HS and LP Oscillator modes. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch ...
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... The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2: Not implemented on PIC16F883/886. DS41291D-page 40 on the R/W-1 R/W-1 (2) ANS4 ANS3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) . Preliminary R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Sleep. The time-out is dependent on the discharge time of the RC circuit on RA0. See Example 3-2 for initializing the Ultra Low-Power Wake-up module. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 A series resistor between RA0 and the external capacitor provides overcurrent protection for the RA0/AN0/ULPWU/C12IN0- pin and can allow for software calibration of the time-out (see Figure 3-1) ...
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... I/O • an analog input for the ADC • a negative analog input to Comparator • an analog input for the Ultra Low-Power Wake- (1) Analog Input Mode ULPWUE To Comparator To A/D Converter Preliminary RA0/AN0/ULPWU/C12IN0 I/O Pin TRG I ULP V SS © 2007 Microchip Technology Inc. ...
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... TRISA RD PORTA To Comparator To A/D Converter Note 1: ANSEL determines Analog Input mode. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 3.2.3.3 RA2/AN2/V Figure 3-3 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • an analog input for the ADC • ...
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... I/O • a clock input for Timer0 • a digital output from Comparator C1 FIGURE 3-5: Data Bus PORTA I/O Pin CK Q TRISA TRISA RD PORTA To Timer0 Preliminary BLOCK DIAGRAM OF RA4 C1OUT Enable V DD C1OUT 1 0 I/O Pin V SS © 2007 Microchip Technology Inc. ...
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... TRISA RD PORTA To SS Input To A/D Converter Note 1: ANSEL determines Analog Input mode. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 3.2.3.7 RA6/OSC2/CLKOUT Figure 3-7 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a crystal/resonator connection • ...
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... C1CH0 0000 -000 0000 -000 C2CH0 0000 -000 0000 -000 C2SYNC 0000 --10 0000 --10 BOR --01 --qq --0u --uu PS0 1111 1111 1111 1111 RA0 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 TRISA0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
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... The following three sections describe these PORTB pin functions. Every PORTB pin on this device family has an interrupt-on-change option and a weak pull-up option. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 3.4.1 ANSELH REGISTER The ANSELH register (Register 3-4) is used to configure the Input mode of an I/O pin to analog ...
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... R/W-1 R/W-1 TRISB4 TRISB3 TRISB2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-1 R/W-1 ANS9 ANS8 bit Bit is unknown R/W-x R/W-x RB1 RB0 bit Bit is unknown R/W-1 R/W-1 TRISB1 TRISB0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 IOCB<7:0>: Interrupt-on-Change PORTB Control bit 1 = Interrupt-on-change enabled 0 = Interrupt-on-change disabled © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-1 R/W-1 R/W-1 WPUB4 WPUB3 WPUB2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... WPUB CCP1OUT Enable D Q CCP1OUT PORTB TRISB RD TRISB RD PORTB IOCB RD IOCB Interrupt-on- Change RD PORTB RB0/INT RB3/PGM To A/D Converter To Comparator (RB1, RB3) Note 1: ANSELH determines Analog Input mode. Preliminary © 2007 Microchip Technology Inc. ( Weak RBPU I/O Pin V SS (1) Analog Input Mode ...
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... Note 1: ANSELH determines Analog Input mode. 2: Applies to RB<7:6> pins only). 3: Applies to RB5 pin only. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 3.4.4.7 RB6/ICSPCLK Figure 3-10 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • ...
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... C2SYNC 0000 --10 0000 --10 IOCB0 0000 0000 0000 0000 RBIF 0000 000x 0000 000x PS0 1111 1111 1111 1111 RB0 xxxx xxxx uuuu uuuu TRISB0 1111 1111 1111 1111 WPUB0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
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... PORTC pin configured as an input (tri-stated PORTC pin configured as an output Note 1: TRISC<1:0> always reads ‘1’ Oscillator mode. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 The TRISC register (Register 3-10) controls the PORTC pin output drivers, even when they are being used as analog inputs ...
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... PWM output • a Capture input and Compare output for Comparator C1 FIGURE 3-13: Data bus PORTC I/O Pin TRISC RD TRISC RD PORTC To Enhanced CCP1 V DD I/O Pin V SS Preliminary BLOCK DIAGRAM OF RC2 CCP1CON CCP1/P1A I/O Pin V SS © 2007 Microchip Technology Inc. ...
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... CK Q PORTC TRISC RD TRISC RD PORTC To SSPSR © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 3.5.6 RC5/SDO Figure 3-16 shows the diagram for this pin. This pin is configurable to function as one of the following: • a general purpose I/O • a serial data output FIGURE 3-16: Data Bus ...
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... CCP1M0 0000 0000 0000 0000 CCP2M0 --00 0000 --00 0000 RC0 xxxx xxxx uuuu uuuu STRA ---0 0001 ---0 0001 RX9D 0000 000x 0000 000x SSPM0 0000 0000 0000 0000 TMR1ON 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
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... TRISD<7:0>: PORTD Tri-State Control bit 1 = PORTD pin configured as an input (tri-stated PORTD pin configured as an output © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 The TRISD register (Register 3-12) controls the PORTD pin output drivers, even when they are being used as analog inputs ...
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... STRC STRB TRISD4 TRISD3 TRISD2 TRISD1 Preliminary (1) (1) BLOCK DIAGRAM OF RD<7:5> PSTRCON CCP1 I/O Pin Value on Value on Bit 0 all other POR, BOR Resets RD0 xxxx xxxx uuuu uuuu STRA ---0 0001 ---0 0001 TRISD0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
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... PORTE pin configured as an input (tri-stated PORTE pin configured as an output Note 1: TRISE<3> always reads ‘1’. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 The TRISE register (Register 3-14) controls the PORTE pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISE register are maintained set when using them as analog inputs ...
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... TRISE3 TRISE2 TRISE1 TRISE0 Preliminary PP BLOCK DIAGRAM OF RE3 V DD MCLRE Weak MCLRE Reset Input Pin V SS MCLRE V SS Value on Value on Bit 0 POR, BOR all other Resets 1111 1111 1111 1111 RE0 ---- xxxx ---- uuuu ---- 1111 ---- 1111 © 2007 Microchip Technology Inc. ...
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... External Oscillator OSC2 Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 The Oscillator module can be configured in one of eight clock modes – External clock with I/O on OSC2/CLKOUT – 32 kHz Low-Power Crystal mode – Medium Gain Crystal or Ceramic Resonator Oscillator mode ...
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... Bit resets to ‘0’ with Two-Speed Start-up and LP selected as the Oscillator mode or Fail-Safe mode is enabled. 41291D-page 62 R/W-0 R-1 R-0 (1) IRCF0 OSTS HTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R-0 R/W-0 LTS SCS bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Upon restarting the external clock, the device will resume operation time had elapsed. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 4.4 External Clock Modes 4 ...
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... DD ® ® and PIC ® Oscillator Design” ® Oscillator CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic P (3) R (2) R Sleep F OSC2/CLKOUT ( may be required for S varies with the Oscillator mode © 2007 Microchip Technology Inc. ...
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... The user also needs to take into account variation due to tolerance of external RC components used. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 4.5 Internal Clock Modes The Oscillator module has two independent, internal oscillators that can be configured or selected as the system clock source ...
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... Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Following any Reset, the IRCF<2:0> bits of the OSCCON register are set to ‘110’ and the frequency selection is set to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 4.5.5 HFINTOSC AND LFINTOSC CLOCK SWITCH TIMING ...
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... IRCF <2:0> System Clock LFINTOSC HFINTOSC LFINTOSC Start-up Time HFINTOSC IRCF <2:0> System Clock 41291D-page 68 Start-up Time 2-cycle Sync = 0 2-cycle Sync = 0 0 LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 ¼ Preliminary Running Running Running © 2007 Microchip Technology Inc. ...
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... Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCCON register to remain clear. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 When the Oscillator module is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 4.4.1 “Oscillator Start-up Timer (OST)” ...
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... FOSC<2:0> bits in the Configuration Word Register 1 (CONFIG1), or the internal oscillator. FIGURE 4-7: TWO-SPEED START-UP HFINTOSC T T OST OSC1 0 1 1022 1023 OSC2 Program Counter System Clock 41291D-page Preliminary © 2007 Microchip Technology Inc. ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<2:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 4.8.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or toggling the SCS bit of the OSCCON register ...
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... BCLIF ULPWUIF — Preliminary Failure Detected Test Value on Value on Bit 0 all other POR, BOR (1) Resets FOSC0 — — SCS -110 x000 -110 x000 TUN0 ---0 0000 ---u uuuu CCP2IE 0000 00-0 0000 00-0 CCP2IF 0000 00-0 0000 00-0 © 2007 Microchip Technology Inc. ...
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... T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register. 2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register. 3: WDTE bit is in the Configuration Word Register1. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 5.1 Timer0 Operation When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter ...
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... Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in the Section 17.0 “Electrical Specifications”. Preliminary © 2007 Microchip Technology Inc. ;Clear WDT and ;prescaler ; ;Mask TMR0 select and ...
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... T0CS TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-1 R/W-1 R/W-1 T0SE PSA U = Unimplemented bit, read as ‘ ...
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... Clock Source F /4 OSC T1CKI pin TMR1ON To C2 Comparator Module Timer1 Clock ( TMR1L 1 T1SYNC ( Prescaler OSC 0 Internal Clock T1CKPS<1:0> TMR1CS Preliminary TMR1CS 0 1 TMR1GE T1GINV Synchronized clock input (3) Synchronize det 2 Sleep input T1G 1 C2OUT 0 T1GSS © 2007 Microchip Technology Inc. ...
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... Note: The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to enabling Timer1. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized ...
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... When using the comparator for Timer1 gate, the comparator output should be synchronized to Timer1. This ensures Timer1 does not miss an increment if the comparator changes. For more information, see Section 8.0 “Comparator Module”. Preliminary © 2007 Microchip Technology Inc. to utilize OSC see Section 11.0 Modules (CCP1 ...
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... Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CM2CON1 register Timer1 gate source. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 R/W-0 R/W-0 T1CKPS0 ...
Page 82
... Bit 0 POR, BOR Resets C2SYNC 0000 --10 0000 --10 RBIF 0000 000x 0000 000x TMR1IE -000 0000 -000 0000 TMR1IF -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1ON 0000 0000 uuuu uuuu © 2007 Microchip Technology Inc. ...
Page 83
... OSC 1:1, 1:4, 1:16 2 T2CKPS<1:0> © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...
Page 84
... Value on Value on Bit 0 all other POR, BOR Resets RBIF 0000 000x 0000 000x TMR1IE -000 0000 -000 0000 TMR1IF -000 0000 -000 0000 1111 1111 1111 1111 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 © 2007 Microchip Technology Inc. ...
Page 85
... Output synchronization to Timer1 clock input • SR Latch • Programmable and fixed voltage reference Note: Only Comparator C2 can be linked to Timer1. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 8.1 Comparator Overview A single comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output ...
Page 86
... IN C2SYNC C2POL D Q From Timer1 Clock Preliminary C1POL To Data Bus RD_CM1CON0 Set C1IF PWM Logic CL C1OUT (to SR Latch) ). OSC C2POL To Data Bus RD_CM2CON0 Set C2IF SYNCC2OUT MUX 1 To Timer1 Gate, SR Latch and other peripherals ). OSC © 2007 Microchip Technology Inc. ...
Page 87
... CxOE bit of the CMxCON0 register must be set • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Note 1: The CxOE bit overrides the PORT data control and latch ...
Page 88
... Comparator module may cause an invalid output from the comparator until the bias circuitry is stable. Allow about 1 μs for bias settling then clear the mismatch condition and interrupt flags before enabling comparator interrupts. Preliminary © 2007 Microchip Technology Inc. reset by software reset by software ...
Page 89
... INTCON register is also set, the device will then execute the Interrupt Service Routine. 8.6 Effects of a Reset A device Reset forces the CMxCON0 and CM2CON1 registers to their Reset states. This forces both comparators and the voltage references to their Off states. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Preliminary DS41291D-page 87 ...
Page 90
... Comparator output requires the following three conditions: C1OE = 1, C1ON = 1 and corresponding port TRIS bit = 0. DS41291D-page 88 R/W-0 U-0 C1POL — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared + > C1V - < C1V - > C1V - < C1V - IN IN (1) output REF - Preliminary R/W-0 R/W-0 R/W-0 C1R C1CH1 C1CH0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 91
... C12IN1- pin of C2 connects to C2V 10 = C12IN2- pin of C2 connects to C2V 11 = C12IN3- pin of C2 connects to C2V Note 1: Comparator output requires the following three conditions: C2OE = 1, C2ON = 1 and corresponding port TRIS bit = 0. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 U-0 C2POL — Unimplemented bit, read as ‘0’ ...
Page 92
... The analog SS 2: Analog levels on any pin defined as a and the DD digital input, may cause the input buffer to consume more current than is specified ≈ 0. LEAKAGE ≈ 0. ±500 nA Vss Preliminary To ADC Input © 2007 Microchip Technology Inc. ...
Page 93
... Timer1 gate source is T1G 0 = Timer1 gate source is SYNCC2OUT. bit 0 C2SYNC: Comparator C2 Output Synchronization bit 1 = Output is synchronous to falling edge of Timer1 clock 0 = Output is asynchronous © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 8.8.2 SYNCHRONIZING COMPARATOR C2 OUTPUT TO TIMER1 The Comparator C2 output can be synchronized with Timer1 by setting the C2SYNC bit of the CM2CON1 register ...
Page 94
... CMxCON0 registers must be set in order to make the comparator or latch outputs available on the output pins. The latch configuration enable states are completely independent of the enable states for the comparators. SR0 0 MUX (1) Latch MUX 0 SR1 Preliminary © 2007 Microchip Technology Inc. C1OE (3) C1OUT pin C2OE (3) C2OUT pin ...
Page 95
... The CxOUT bit in the CMxCON0 register will always reflect the actual comparator output (not the level on the pin), regardless of the SR latch operation enable an SR Latch output to the pin, the appropriate CxOE and TRIS bits must be properly configured. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 R/S-0 R/S-0 ...
Page 96
... Preliminary SS module current. REF derived and DD output changes with fluctuations in REF , with DD or fixed REF voltage divider and selects REF voltage divider and selects REF voltage divider is disabled REF © 2007 Microchip Technology Inc. ...
Page 97
... ADC Module Note 1: Care should be taken when using V FIGURE 8-9: COMPARATOR AND ADC VOLTAGE REFERENCE BLOCK DIAGRAM V + REF VROE VCFG1 VRSS REF © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 16 Stages Analog MUX 15 0 (1) VR<3:0> 0.6V Fixed Voltage Reference - with Comparator. REF AV DD ...
Page 98
... REF REF DS41291D-page 96 Comp. ADC ADC Reference (+) Reference (-) REF REF REF REF REF REF REF REF REF DD REF V - AVDD VREF- REF REF REF REF REF REF REF REF REF REF REF Preliminary CFG1 CFG0 VRSS VROE © 2007 Microchip Technology Inc. ...
Page 99
... TRISB6 TRISB5 VRCON VREN VROE VRR Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 R/W-0 R/W-0 VRSS VR3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 100
... PIC16F882/883/884/886/887 NOTES: DS41291D-page 98 Preliminary © 2007 Microchip Technology Inc. ...
Page 101
... AN6 AN7 0111 1000 AN8 1001 AN9 1010 AN10 AN11 1011 AN12 1100 1101 AN13 CV 1110 REF Fixed Ref 1111 CHS<3:0> © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 (ADC) allows VCFG1 = VCFG1 = VCFG0 = 0 VCFG0 = 1 ADC GO/DONE ADFM ADON V SS Preliminary Left Justify ...
Page 102
... Section 17.0 “Electrical Specifications” for more information. Table 9-1 gives examples of appropriate ADC clock selections. Note: Unless using the F system clock frequency will change the ADC clock adversely affect the ADC result. Preliminary © 2007 Microchip Technology Inc periods AD specification AD , any changes in the RC frequency, ...
Page 103
... Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine. Please see Section 14.3 “Interrupts” for more information. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 ) V . DEVICE OPERATING FREQUENCIES (VDD > 3.0V ...
Page 104
... ADC timing the user’s responsibility to ensure that the ADC timing requirements are met. See Section 11.0 “Capture/Compare/PWM Modules (CCP1 and CCP2)” for more information. Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 RC clock source is selected, the RC © 2007 Microchip Technology Inc. ...
Page 105
... Sleep and resume in-line code execution. 2: See Section 9.3 “A/D Requirements”. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 EXAMPLE 9-1: ;This code block configures the ADC ;for polling, Vdd and Vss as reference, Frc clock and AN0 input. ...
Page 106
... ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current DS41291D-page 104 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 GO/DONE ADON bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 107
... V - pin REF bit 4 VCFG0: Voltage Reference bit pin REF bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 U-0 U-0 VCFG0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — ...
Page 108
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-x R/W-x ADRES3 ADRES2 bit Bit is unknown R/W-x R/W-x — — bit Bit is unknown R/W-x R/W-x ADRES9 ADRES8 bit Bit is unknown R/W-x R/W-x ADRES1 ADRES0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 109
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin leakage specification. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 9-1 may be used ...
Page 110
... REF DS41291D-page 108 V DD Sampling Switch V = 0.6V T ≤ Rss LEAKAGE V = 0.6V T ± 500 Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal Zero-Scale REF Transition Preliminary HOLD REF Sampling Switch (kΩ) © 2007 Microchip Technology Inc. ...
Page 111
... TRISA5 TRISB TRISB7 TRISB6 TRISB5 TRISE — — — Legend unknown unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE VCFG0 — ...
Page 112
... PIC16F882/883/884/886/887 NOTES: DS41291D-page 110 Preliminary © 2007 Microchip Technology Inc. ...
Page 113
... EECON2 • EEDAT • EEDATH • EEADR • EEADRH (bit 4 on PIC16F886/PIC16F887 only) When interfacing the data memory block, EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EEDAT location being accessed. These devices have 256 bytes of data EEPROM with an address range from 0h to 0FFh ...
Page 114
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 EEADRH<4:0>: Specifies the 4 Most Significant Address bits or high bits for program memory reads Note 1: PIC16F886/PIC16F887 only. DS41291D-page 112 R/W-0 R/W-0 R/W-0 EEDAT4 EEDAT3 EEDAT2 U = Unimplemented bit, read as ‘0’ ...
Page 115
... Write cycle to the data EEPROM is complete bit 0 RD: Read Control bit 1 = Initiates a memory read (the RD is cleared in hardware and can only be set, not cleared, in software Does not initiate a memory read © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 U-0 R/W-x R/W-0 — WRERR WREN U = Unimplemented bit, read as ‘ ...
Page 116
... WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software. Preliminary © 2007 Microchip Technology Inc. ...
Page 117
... EEDATH, W MOVWF HIGHPMBYTE BCF STATUS, RP1 © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 EEDAT and EEDATH registers will hold this value until another read or until it is written to by the user. Note 1: The two instructions following a program memory read are required to be NOPs. ...
Page 118
... Flash Data INSTR (PC) BSF EECON1,RD INSTR( executed here executed here RD bit EEDATH EEDAT Register EERHLT DS41291D-page 116 EEADRH,EEADR PC+3 INSTR ( EEDATH,EEDAT INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( INSTR( INSTR( executed here executed here © 2007 Microchip Technology Inc. ...
Page 119
... Microchip Technology Inc. PIC16F882/883/884/886/887 After the “BSF EECON1,WR” instruction, the processor requires two cycles to set up the erase/write operation. ...
Page 120
... Flash automatically after this word is written 14 14 EEADR<1:0> Buffer Register 0 Sixteen words of Flash are erased, then eight buffers 8 are transferred to Flash automatically after this word is written 14 14 EEADR<2:0> = 111 Buffer Register © 2007 Microchip Technology Inc. ...
Page 121
... STATUS,RP0 INCF EEADR,F MOVF EEADR,W ANDLW 0x07 XORLW 0x07 BTFSC STATUS,Z GOTO LOOP © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 ; ; Bank 2 ; Load initial address ; ; ; ; Load initial data address ; ; Load first data byte into lower ; ; Next byte ; Load second data byte into upper ...
Page 122
... NOPs) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. Programming unused locations in program memory to ‘0’ will also help prevent data memory code protection from becoming breached. prevents Preliminary © 2007 Microchip Technology Inc. ...
Page 123
... C1IE PIR2 OSFIF C2IF C1IF Legend unknown unchanged, — = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by data EEPROM module. Note 1: PIC16F886/PIC16F887 only. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Bit 4 Bit 3 Bit 2 Bit 1 — WRERR WREN ...
Page 124
... PIC16F882/883/884/886/887 NOTES: DS41291D-page 122 Preliminary © 2007 Microchip Technology Inc. ...
Page 125
... Enhanced PWM features available on CCP1 only. See Section 11.6 “PWM (Enhanced Mode)” for more information. Note: CCPRx and CCPx throughout document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 this Preliminary DS41291D-page 123 ...
Page 126
... ECCP MODE – TIMER RESOURCES REQUIRED ECCP Mode Capture Compare PWM R/W-0 R/W-0 R/W-0 DC1B0 CCP1M3 CCP1M2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 CCP1M1 CCP1M0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 127
... Compare mode, generate software interrupt on match (CCP2IF bit is set, CCP2 pin is unaffected) 1011 = Compare mode, trigger special event (CCP2IF bit is set, TMR1 is reset and A/D conversion is started if the ADC module is enabled. CCP2 pin is unaffected.) 11xx = PWM mode. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 TABLE 11-2: CCP MODE – TIMER RESOURCES REQUIRED ...
Page 128
... MOVLW NEW_CAPT_PS ;Load the W reg with CCPRxL MOVWF CCP1CON TMR1L Preliminary CHANGING BETWEEN CAPTURE PRESCALERS ;Set Bank bits to point ;to CCP1CON ;Turn CCP module off ; the new prescaler ; move value and CCP ON ;Load CCP1CON with this ; value © 2007 Microchip Technology Inc. ...
Page 129
... Note: Clearing the CCP1CON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 11.4.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode ...
Page 130
... DS41291D-page 128 The PWM output (Figure 11-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 11-4: Period Pulse Width TMR2 = 0 CCPx TRIS ), or OSC Preliminary CCP PWM OUTPUT TMR2 = PR2 TMR2 = CCPRxL:CCPxCON<5:4> © 2007 Microchip Technology Inc. ...
Page 131
... CCPRxH. Note: The Timer2 postscaler (see Section 7.1 “Timer2 Operation”) is not used in the determination of the PWM frequency. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 11.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB< ...
Page 132
... OSC 4.90 kHz 19.61 kHz 76.92 kHz 0x65 0x65 0x19 Preliminary [ ( ) ] log 4 PR2 + 1 ----------------------------------------- - bits log = 20 MHz) 156.3 kHz 208.3 kHz 1 1 0x1F 0x17 7 6 MHz) 153.85 kHz 200.0 kHz 1 1 0x0C 0x09 5 5 © 2007 Microchip Technology Inc. ...
Page 133
... Clock Monitor)” for additional details. 11.5.6 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 11.5.7 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1 ...
Page 134
... Output Q Controller P1C TRISn P1D TRISn PWM1CON CCP1/P1A P1B (1) (1) Yes Yes Yes Yes Yes Yes Yes Yes Preliminary the generation of an CCP1/P1A P1B P1C P1D P1C P1D (1) (1) Yes Yes No No Yes Yes Yes Yes © 2007 Microchip Technology Inc. ...
Page 135
... OSC • Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.6.6 “Programmable Dead-Band Delay Mode”). © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Pulse 0 Width Period (1) (1) Delay Delay ...
Page 136
... Pulse Width = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (PWM1CON<6:0>) OSC Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.6.6 “Programmable Dead-Band Delay Mode”). DS41291D-page 134 Pulse 0 Width Period (1) (1) Delay Delay Preliminary © 2007 Microchip Technology Inc. PR2+1 ...
Page 137
... Standard Half-Bridge Circuit (“Push-Pull”) Half-Bridge Output Driving a Full-Bridge Circuit P1A P1B © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Since the P1A and P1B outputs are multiplexed with the PORT data latches, the associated TRIS bits must be cleared to configure P1A and P1B as outputs. ...
Page 138
... P1A, P1B, P1C and P1D outputs are multiplexed with the PORT data latches. The associated TRIS bits must be cleared to configure the P1A, P1B, P1C and P1D pins as outputs FET Driver Load FET Driver QB V- Preliminary QC FET Driver FET Driver QD © 2007 Microchip Technology Inc. ...
Page 139
... Forward Mode (2) P1A Pulse Width (2) P1B (2) P1C (2) P1D (1) Reverse Mode Pulse Width (2) P1A (2) P1B (2) P1C (2) P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signal is shown as active-high. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Period (1) Period (1) Preliminary DS41291D-page 137 ...
Page 140
... Reduce PWM duty cycle for one PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. (1) Period Pulse Width (2) Preliminary Period © 2007 Microchip Technology Inc. ...
Page 141
... External Switch C External Switch D Potential Shoot-Through Current Note 1: All signals are shown as active-high the turn on delay of power switch QC and its driver the turn off delay of power switch QD and its driver. OFF © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Forward Period Reverse Period Preliminary PW ...
Page 142
... Output mode and complete a full PWM cycle before enabling the PWM pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF bit of the PIR1 register being set as the second PWM period begins. DS41291D-page 140 Preliminary © 2007 Microchip Technology Inc. ...
Page 143
... Drive pins P1B and P1D to ‘1’ Pins P1B and P1D tri-state Note 1: If C2SYNC is enabled, the shutdown will be delayed by Timer1. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 A shutdown condition is indicated by the ECCPASE (Auto-Shutdown Event Status) bit of the ECCPAS register. If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘ ...
Page 144
... Activity Start of PWM Period DS41291D-page 142 is a condition PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears Preliminary ECCPASE Cleared by Firmware PWM Resumes PWM Resumes © 2007 Microchip Technology Inc. ...
Page 145
... The lower seven bits of the associated PWM1CON register (Register 11-4) sets the delay period in terms of microcontroller instruction cycles ( OSC FIGURE 11-17: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 FIGURE 11-16: Period Pulse Width (2) P1A td (2) P1B (1) ...
Page 146
... DS41291D-page 144 R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared / cycles between the scheduled time when a PWM signal OSC OSC Preliminary R/W-0 R/W-0 R/W-0 PDC2 PDC1 PDC0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 147
... P1A pin is assigned to port pin Note 1: The PWM Steering mode is available only when the CCP1CON register bits CCP1M<3:2> and P1M<1:0> = 00. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Note: The associated TRIS bits must be set to output (‘0’) to enable the pin output driver in order to see the PWM signal on the pin. While the PWM Steering mode is active, CCP1M< ...
Page 148
... Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> and CCP1M<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. DS41291D-page 146 P1A pin P1B pin P1C pin P1D pin Preliminary © 2007 Microchip Technology Inc. ...
Page 149
... PORT Data FIGURE 11-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) PWM STRn P1<D:A> PORT Data © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Figures 11-19 and 11-20 illustrate the timing diagrams of the PWM steering depending on the STRSYNC setting. PORT Data P1n = PWM P1n = PWM ...
Page 150
... STRA ---0 0001 ---0 0001 PDC0 0000 0000 0000 0000 T2CKPS0 -000 0000 -000 0000 0000 0000 0000 0000 TRISB0 1111 1111 1111 1111 TRISC0 1111 1111 1111 1111 TRISD0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
Page 151
... SPBRGH SPBRG BRGH BRG16 © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 The EUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length • Address detection in 9-bit mode • ...
Page 152
... Register 12-2 and Register 12-3, respectively. DS41291D-page 150 MSb Data Stop Recovery F OSC ÷ x16 x64 0 0 FERR 0 Register 12-1, Preliminary CREN OERR RCIDL RSR Register LSb • • • ( Start RX9 FIFO RX9D RCREG Register 8 Data Bus RCIF Interrupt RCIE © 2007 Microchip Technology Inc. ...
Page 153
... TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral the analog I/O function must be disabled by clearing the corresponding ANSEL bit. © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 Note 1: When the SPEN bit is set the RX/DT I/O pin is automatically configured as an input, ...
Page 154
... TX9D data bit. 7. Load 8-bit data into the TXREG register. This will start the transmission. bit 0 bit 1 bit 7/8 Word 1 bit 0 bit 1 bit 7/8 Word Preliminary Stop bit Start bit bit 0 Stop bit Word 2 Word 2 Transmit Shift Reg. © 2007 Microchip Technology Inc. ...
Page 155
... TRISC6 TRISC5 TXREG EUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Transmission. © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 Bit 4 Bit 3 Bit 2 Bit 1 SCKP BRG16 — WUE INTE ...
Page 156
... PEIE peripheral interrupt enable bit of the INTCON register • GIE global interrupt enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. Preliminary © 2007 Microchip Technology Inc. ...
Page 157
... FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 12.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems ...
Page 158
... If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Start bit 7/8 bit 7/8 Stop Stop bit bit 0 bit bit Word 2 Word 1 RCREG RCREG Preliminary Start bit Stop bit 7/8 bit © 2007 Microchip Technology Inc. ...
Page 159
... TRISC6 TRISC5 TXREG EUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Asynchronous Reception. © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 Bit 4 Bit 3 Bit 2 Bit 1 SCKP BRG16 — WUE INTE ...
Page 160
... Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. R/W-0 R/W-0 (1) SYNC SENDB U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-1 R/W-0 BRGH TRMT TX9D bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 161
... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 R/W-0 R/W-0 R-0 CREN ...
Page 162
... Auto-Baud Detect mode is enabled (clears when auto-baud is complete Auto-Baud Detect mode is disabled Synchronous mode: Don’t care DS41291D-page 160 R/W-0 R/W-0 U-0 SCKP BRG16 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 WUE ABDEN bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 163
... TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator. © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is Idle before changing the system clock ...
Page 164
... F = 8.000 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) — — — — — — — — 2404 0.16 207 — 71 9615 0. 10417 0. 19231 0. 55556 -3. — — — © 2007 Microchip Technology Inc. ...
Page 165
... Microchip Technology Inc. PIC16F822/883/884/886/887 SYNC = 0, BRGH = 1, BRG16 = 3.6864 MHz F = 2.000 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — ...
Page 166
... F = 1.000 MHz OSC SPBRG SPBRG Actual % value value Rate Error (decimal) (decimal) 1666 300.1 0.04 832 416 1202 0.16 207 207 2404 0.16 103 51 9615 0. 10417 0. 19.23k 0. — — — — — — — © 2007 Microchip Technology Inc. ...
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... SPBRG SPBRGH Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. ...
Page 168
... WUE bit receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. Cleared due to User Read of RCREG Preliminary © 2007 Microchip Technology Inc. Auto Cleared ...
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... After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 Q1Q2 Q3 Q4 Cleared due to User Read of RCREG Sleep Ends 12 ...
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... Clock) TX (pin) Start bit TXIF bit (Transmit interrupt Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB SENDB (send Break control bit) DS41291D-page 168 bit 0 bit 1 bit 11 Break Sampled Here Preliminary Stop bit Auto Cleared © 2007 Microchip Technology Inc. ...
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... A clock polarity option is provided for Microwire compatability. Clock polarity is selected with the SCKP bit of the BAUDCTL register. Setting the SCKP bit sets © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. ...
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... RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 BRG8 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 © 2007 Microchip Technology Inc. ...
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... Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG. © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 12.4.1.8 Synchronous Master Reception Set- up: 1 ...
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... RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 BRG8 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 © 2007 Microchip Technology Inc. ...
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... CSRC TX9 TXEN Legend unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. © 2007 Microchip Technology Inc. PIC16F822/883/884/886/887 If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. ...
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... RX9D 0000 000x 0000 000x BRG0 0000 0000 0000 0000 BRG8 0000 0000 0000 0000 TRISC0 1111 1111 1111 1111 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 © 2007 Microchip Technology Inc. ...
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... These include a STATUS register and two control registers. Register 13-1 shows the MSSP STATUS register (SSPSTAT), Register 13-2 shows the MSSP Control Register 1 (SSPCON), and Register 13-3 shows the MSSP Control Register 2 (SSPCON2). © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Preliminary DS41291D-page 175 ...
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... Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty DS41291D-page 176 R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C mode only mode only) Preliminary R-0 R bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 179
... Reserved 1101 = Reserved 2 1110 = I C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with Start and Stop bit interrupts enabled © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘ ...
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... C Master mode only Master mode only Master mode only Master mode only Master mode only Master mode only module is not in the Idle mode, this bit may not be Preliminary R/W-0 R/W-0 RSEN SEN bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Clock edge (output data on rising/falling edge of SCK) • Clock rate (Master mode only) • Slave Select mode (Slave mode only) Figure 13-1 shows the block diagram of the MSSP module, when in SPI mode. © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 FIGURE 13-1: Read SDI bit 0 ...
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... SCK (Slave mode) must have TRISC<3> bit set • SS must have TRISA<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. Preliminary © 2007 Microchip Technology Inc. ...
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... Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 The clock polarity is selected by appropriately program- ming the CKP bit of the SSPCON register. This, then, would give waveforms for SPI communication as shown in Figure 13-2, Figure 13-4 and Figure 13-5, where the MSb is transmitted first ...
Page 184
... SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function), since it cannot create a bus conflict. bit 6 bit 7 bit 7 Preliminary . DD bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
Page 185
... CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF bit 7 SDO SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 bit 6 bit 2 bit 5 bit 4 bit 3 bit 6 bit 5 bit 4 bit 2 bit 3 Preliminary bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ ...
Page 186
... TMR1IE 0000 0000 0000 0000 0000 0000 TMR1IF -000 0000 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 BF 0000 0000 0000 0000 TRISA0 1111 1111 1111 1111 TRISC0 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
Page 187
... MSSP Shift Register (SSPSR) – Not directly accessible • MSSP Address register (SSPADD) • MSSP Mask register (SSPMSK) © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 The SSPCON register allows control of the I operation. The SSPM<3:0> mode selection bits (SSPCON register) allow one of the following I ...
Page 188
... Start bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Pin RC3/SCK/SCL should be enabled by setting bit CKP. Preliminary © 2007 Microchip Technology Inc. ...
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... S SSPIF BF SSPOV 2 FIGURE 13-8: I C™ SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address SDA SCL Data in Sampled SSPIF BF CKP © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Receiving Data ACK ACK Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full ...
Page 190
... Acknowledge (Figure 13-9). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Preliminary Receiving Data ACK ‘0’ ‘1’ © 2007 Microchip Technology Inc. ...
Page 191
... MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision Note: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 2 13.4.4 I C™ MASTER MODE SUPPORT Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit ...
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... The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. k) The user generates a Stop condition by setting the Stop Enable bit PEN (SSPCON2 register). l) Interrupt is generated once the Stop condition is complete. Preliminary © 2007 Microchip Technology Inc. ...
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... FIGURE 13-12: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG 03h Value BRG Reload © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 ) on the CY SSPM<3:0> SSPADD<6:0> Reload Reload Control BRG Down Counter CLKOUT DX-1 ...
Page 194
... SSPCON2 is disabled until the Start condi- tion is complete Set S bit (SSPSTAT) SDA = 1, At completion of Start bit, SCL = 1 hardware clears SEN bit and sets SSPIF bit T T BRG BRG Write to SSPBUF occurs here 1st Bit T BRG S Preliminary 2nd Bit T BRG © 2007 Microchip Technology Inc. ...
Page 195
... SDA = 1, SCL (no change) SDA Falling edge of ninth clock End of Xmit SCL © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Note 1: If RSEN is programmed while any other event is in progress, it will not take effect bus collision during the Repeated Start condition occurs if: • ...
Page 196
... If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). Preliminary © 2007 Microchip Technology Inc. Enable bit ACKEN ...
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... FIGURE 13-15: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 Preliminary DS41291D-page 195 ...
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... PIC16F882/883/884/886/887 2 FIGURE 13-16: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS41291D-page 196 Preliminary © 2007 Microchip Technology Inc. ...
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... SSPIF Set SSPIF at the end of receive Note one Baud Rate Generator period. BRG © 2007 Microchip Technology Inc. PIC16F882/883/884/886/887 13.4.11 STOP CONDITION TIMING A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2 register). At the end of a receive/transmit, the SCL line is held low after the fall- ing edge of the ninth clock ...
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... A Reset disables the MSSP module and terminates the current transfer. SCL = 1, BRG starts counting clock high interval SCL line sampled once every machine cycle (T Hold off BRG until SCL is sampled high T T BRG BRG Preliminary BRG 2 C module can receive *4), OSC © 2007 Microchip Technology Inc. ...