PIC16F887-I/PT Microchip Technology Inc., PIC16F887-I/PT Datasheet - Page 117

• Manufacturer Part Number: PIC16F887-I/PT
• Description: MCU, 8-Bit, 8KW Flash, 368 RAM, 36 I/O, TQFP-44
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F887-I/PT

• A/d Inputs: 14-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Frequency: 20 MHz
• Input Output: 35
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TFQP
• Programmable Memory: 14K Bytes
• Ram Size: 368 Bytes
• Resistance, Drain To Source On: Bytes
• Serial Interface: MSSP or EUSART
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

10.1.4
To read a program memory location, the user must
write the Least and Most Significant address bits to the
EEADR and EEADRH registers, set the EEPGD con-
trol bit of the EECON1 register, and then set control bit
RD. Once the read control bit is set, the program mem-
ory Flash controller will use the second instruction
cycle to read the data. This causes the second instruc-
tion immediately following the “BSF
instruction to be ignored. The data is available in the
very next cycle, in the EEDAT and EEDATH registers;
therefore, it can be read as two bytes in the following
instructions.
EXAMPLE 10-3:
© 2007 Microchip Technology Inc.
;
;
BANKSEL EEADR
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL EECON1
BSF
BSF
NOP
NOP
BANKSEL EEDAT
MOVF
MOVWF
MOVF
MOVWF
BCF
READING THE FLASH PROGRAM
MEMORY
MS_PROG_EE_ADDR
EEADRH
LS_PROG_EE_ADDR
EEADR
EECON1, EEPGD
EECON1, RD
EEDAT, W
LOWPMBYTE
EEDATH, W
HIGHPMBYTE
STATUS, RP1
FLASH PROGRAM READ
EECON1,RD”
;
;
;MS Byte of Program Address to read
;
;LS Byte of Program Address to read
;
;Point to PROGRAM memory
;EE Read
;First instruction after BSF EECON1,RD executes normally
;Any instructions here are ignored as program
;memory is read in second cycle after BSF EECON1,RD
;
;W = LS Byte of Program Memory
;
;W = MS Byte of Program EEDAT
;
;Bank 0
PIC16F882/883/884/886/887
Preliminary
EEDAT and EEDATH registers will hold this value until
another read or until it is written to by the user.
Note 1: The two instructions following a program
2: If the WR bit is set when EEPGD = 1, it
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle
instruction after the RD bit is set.
will be immediately reset to ‘0’ and no
operation will take place.
instruction
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