PIC16F72-I/SP Microchip Technology Inc., PIC16F72-I/SP Datasheet
PIC16F72-I/SP
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PIC16F72-I/SP Summary of contents
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... Microcontroller with A/D Converter 2002 Microchip Technology Inc. M Data Sheet 28-Pin, 8-Bit CMOS FLASH PIC16F72 DS39597B ...
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... QS-9000 compliant for its PICmicro ® 8-bit MCUs ® code hopping EE OQ devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. ...
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... M 28-Pin, 8-Bit CMOS FLASH MCU with A/D Converter Device Included: • PIC16F72 High Performance RISC CPU: • Only 35 single word instructions to learn • All single cycle instructions except for program branches, which are two-cycle • Operating speed MHz clock input DC - 200 ns instruction cycle • ...
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... FLASH Program Memory - (14-bit words, 1000 E/W cycles) Data Memory - RAM (8-bit bytes) Interrupts I/O Ports Timers Capture/Compare/PWM Modules Serial Communications 8-bit A/D Converter Instruction Set (No. of Instructions) DS39597B-page 2 PIC16F72 MHz POR, BOR, (PWRT, OST) 2K 128 8 PORTA, PORTB, PORTC Timer0, Timer1, Timer2 1 SSP ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2002 Microchip Technology Inc. PIC16F72 DS39597B-page 3 ...
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... PIC16F72 NOTES: DS39597B-page 4 2002 Microchip Technology Inc. ...
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... The PIC16F72 belongs to the Mid-Range family of the PICmicro devices. A block diagram of the device is shown in Figure 1-1. FIGURE 1-1: PIC16F72 BLOCK DIAGRAM ...
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... PIC16F72 TABLE 1-1: PIC16F72 PINOUT DESCRIPTION PDIP, SOIC, MLF I/O/P Pin Name SSOP Pin# Type Pin# OSC1/CLKI OSC2/CLKO I/P MCLR/V PP RA0/AN0 2 27 I/O RA1/AN1 3 28 I/O RA2/AN2 4 1 I/O RA3/AN3 I/O REF RA4/T0CKI 6 3 I/O RA5/AN4/ I/O RB0/INT 21 18 I/O RB1 ...
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... MEMORY ORGANIZATION There are two memory blocks in the PIC16F72 device. These are the program memory and the data memory. Each block has separate buses so that concurrent access can occur. Program memory and data memory are explained in this section. Program memory can be read internally by the user code (see Section 4 ...
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... PIC16F72 FIGURE 2-2: PIC16F72 REGISTER FILE MAP File Address Indirect addr.(*) Indirect addr.(*) 00h TMR0 01h 02h PCL STATUS 03h FSR 04h 05h PORTA 06h PORTB PORTC 07h 08h 09h PCLATH 0Ah INTCON 0Bh 0Ch PIR1 0Dh TMR1L 0Eh 0Fh TMR1H ...
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... Write Buffer for the upper 5 bits of the Program Counter INTE RBIE TMR0IF — — SSPIF CCP1IF CKP SSPM3 SSPM2 CCP1Y CCP1M3 CCP1M2 CHS2 CHS1 CHS0 GO/DONE PIC16F72 Value on Details on Bit 1 Bit 0 POR, BOR page: 19 29,13 xxxx xxxx 18 0000 0000 0001 1xxx 19 xxxx xxxx ...
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... PIC16F72 TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 1 (1) 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 81h OPTION RBPU INTEDG (1) 82h PCL Program Counter’s (PC) Least Significant Byte ...
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... Address Register High Byte T0CS T0SE PSA PS2 RP0 Write Buffer for the upper 5 bits of the Program Counter — INTE RBIE TMR0IF — — — — PIC16F72 Value on Details on Bit 1 Bit 0 POR, BOR page xxxx xxxx 18 0000 0000 0001 1xxx 19 xxxx xxxx — ...
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... PIC16F72 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS ...
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... TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 1 : 128 1 : 256 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F72 R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown DS39597B-page 13 ...
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... PIC16F72 2.2.2.3 INTCON Register The INTCON Register is a readable and writable regis- ter that contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh) ...
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... R = Readable bit - n = Value at POR 2002 Microchip Technology Inc. U-0 U-0 R/W-0 R/W-0 — — SSPIE CCP1IE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F72 R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown DS39597B-page 15 ...
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... PIC16F72 2.2.2.5 PIR1 Register This register contains the individual flag bits for the Peripheral interrupts. REGISTER 2-5: PIR1: PERIPHERAL INTERRUPT FLAG REGISTER 1 (ADDRESS 0Ch) U-0 R/W-0 — ADIF bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 ADIF: A/D Converter Interrupt Flag bit ...
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... BOREN bit in the Configuration word). U-0 U-0 U-0 — — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F72 U-0 R/W-0 R/W-x — POR BOR bit Bit is unknown DS39597B-page 17 ...
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... PIC16F72 2.3 PCL and PCLATH The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 13-bits wide. The low byte is called the PCL register. This reg- ister is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> ...
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... PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the return instructions (which POPs the address from the stack). Note: The PIC16F72 device ignores the paging bit PCLATH<4:3>. The PCLATH<4:3> general purpose read/ ...
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... PIC16F72 FIGURE 2-5: DIRECT/INDIRECT ADDRESSING Direct Addressing From Opcode RP1:RP0 6 Bank Select Location Select 00h Data (1) Memory 7Fh Bank 0 Note 1: For register file map detail, see Figure 2-2. DS39597B-page 20 0 IRP Bank Select 80h 100h 180h FFh 17Fh 1FFh Bank 1 Bank 2 ...
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... MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as ‘0’. 2002 Microchip Technology Inc. PIC16F72 FIGURE 3-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Data Bus Port CK Q ...
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... PIC16F72 TABLE 3-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit 0 TTL RA1/AN1 bit 1 TTL RA2/AN2 bit 2 TTL RA3/AN3/V bit 3 TTL REF RA4/T0CKI bit 4 ST RA5/AN4/SS bit 5 TTL Legend: TTL = TTL input Schmitt Trigger input TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA ...
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... TRIS Latch TRIS CK RD TRIS RD Port Set RBIF From Other RB7:RB4 Pins RB7:RB6 in Serial Programming Mode Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION<7>). PIC16F72 BLOCK DIAGRAM OF RB7:RB4 PINS Weak Pull-up Q I/O pin ...
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... PIC16F72 TABLE 3-3: PORTB FUNCTIONS Name Bit# Buffer (1) RB0/INT bit 0 TTL/ST RB1 bit 1 TTL RB2 bit 2 TTL RB3 bit 3 TTL RB4 bit 4 TTL RB5 bit 5 TTL (2) RB6 bit 6 TTL/ST (2) RB7 bit 7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. ...
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... Select Bank for TRISC MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs 2002 Microchip Technology Inc. PIC16F72 FIGURE 3-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) (1) Port/Peripheral Select Peripheral Data Out 0 Data Bus D ...
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... PIC16F72 TABLE 3-5: PORTC FUNCTIONS Name Bit# Buffer Type bit 0 RC0/T1OSO/T1CKI ST RC1/T1OSI bit 1 ST RC2/CCP1 bit 2 ST RC3/SCK/SCL bit 3 ST RC4/SDI/SDA bit 4 ST RC5/SDO bit 5 ST RC6 bit 6 ST RC7 bit 7 ST Legend Schmitt Trigger input TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC ...
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... It is cleared in hardware at the completion of the read operation. reads. The U-0 U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ Settable bit ‘0’ = Bit is cleared PIC16F72 U-0 U-0 R/S-0 — — — RD bit Value at POR x = Bit is unknown DS39597B-page 27 ...
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... PIC16F72 4.3 Reading the FLASH Program Memory To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers and then set control bit, RD (PMCON1<0>). Once the read control bit is set, the program memory FLASH controller will use the second instruction cycle after to read the data. This causes the second instruction immediately following the “ ...
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... Interrupt Service Routine, before re-enabling this inter- rupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP SYNC Cycles PSA PRESCALER 8-bit Prescaler 1MUX PS2:PS0 PSA WDT Time-out PIC16F72 Data Bus 8 TMR0 reg Set Flag bit TMR0IF on Overflow DS39597B-page 29 ...
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... PIC16F72 5.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... RESET can be generated by the CCP module (Section 8.0). U-0 R/W-0 R/W-0 R/W-0 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F72 R/W-0 R/W-0 R/W-0 bit Bit is unknown DS39597B-page 31 ...
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... PIC16F72 6.2 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is F /4. The synchronize control bit T1SYNC OSC (T1CON<2>) has no effect, since the internal clock is always in sync. 6.3 Timer1 Counter Operation Timer1 may operate in Asynchronous or Synchronous mode, depending on the setting of the TMR1CS bit ...
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... Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up. 2002 Microchip Technology Inc. PIC16F72 TABLE 6-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq ...
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... PIC16F72 6.9 Resetting Timer1 Register Pair (TMR1H, TMR1L) TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale ...
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... Sets Flag TMR2 bit TMR2IF Output RESET control bits Postscaler 1:1 to 1:16 4 Note 1: TMR2 register output can be software selected by the SSP module as a baud clock. PIC16F72 TIMER2 BLOCK DIAGRAM (1) Prescaler TMR2 reg F /4 OSC 1:1, 1:4, 1:16 2 Comparator EQ PR2 reg DS39597B-page 35 ...
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... PIC16F72 REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • ...
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... Compare PWM R/W-0 R/W-0 R/W-0 — CCPxX CCPxY CCPxM3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F72 CCP MODE - TIMER RESOURCE Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 R/W-0 CCPxM2 CCPxM1 CCPxM0 bit 0 ...
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... PIC16F72 8.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON< ...
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... Timer1. The special trigger output of CCP1 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>). Comparator TMR1H TMR1L PIC16F72 DS39597B-page 39 ...
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... PIC16F72 TABLE 8-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1 Address Name Bit 7 Bit 6 0Bh,8Bh INTCON GIE PEIE TMR0IE 10Bh,18Bh 0Ch PIR1 — ADIF 8Ch PIE1 — ADIE 87h TRISC PORTC Data Direction Register 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register ...
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... PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. PIC16F72 PWM PERIOD • OSC (TMR2 prescale value) ...
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... PIC16F72 Maximum PWM resolution (bits) for a given PWM frequency is calculated using Equation 8-3. EQUATION 8-3: PWM MAX RESOLUTION F log ( F PWM Maximum Resolution = log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. For a sample PWM period and duty cycle calculation, see the PICmicro™ ...
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... Slave mode (SCK is the clock input) • Clock Polarity (IDLE state of SCK) • Clock edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) PIC16F72 register definitions and RC5/SDO RC4/SDI/SDA RC3/SCK/SCL ...
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... PIC16F72 REGISTER 9-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 SMP CKE bit 7 bit 7 SMP: SPI Data Input Sample Phase bits SPI Master mode Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire ...
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... Microchip Technology Inc. R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 ® default) /4 OSC /16 OSC /64 OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared PIC16F72 R/W-0 R/W-0 R/W-0 SSPM1 SSPM0 bit Bit is unknown DS39597B-page 45 ...
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... PIC16F72 FIGURE 9-1: SSP BLOCK DIAGRAM (SPI MODE) Read SSPBUF reg SSPSR reg RC4/SDI/SDA bit0 RC5/SDO SS Control Enable RA5/AN4/SS Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TRISC<3> TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION Address Name Bit 7 Bit 6 0Bh,8Bh ...
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... SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 SDI (SMP = 0) bit7 SSPIF 2002 Microchip Technology Inc. bit6 bit5 bit4 bit3 bit6 bit5 bit3 bit4 bit2 bit5 bit3 bit4 PIC16F72 bit2 bit1 bit0 bit0 bit0 bit2 bit1 bit0 bit0 bit1 bit0 bit0 DS39597B-page 47 ...
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... PIC16F72 2 9.3 SSP I C Mode Operation 2 The SSP module mode fully implements all slave functions, except general call support and provides interrupts on START and STOP bits in hardware to facilitate firmware implementations of the master func- tions. The SSP module implements the Standard mode specifications, as well as 7-bit and 10-bit addressing ...
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... SSPBUF register, which also loads the SSPSR reg- ister. Then, pin RC3/SCK/SCL should be enabled by setting bit CKP. SSPBUF Generate ACK Pulse Yes PIC16F72 Transmission Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes DS39597B-page 49 ...
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... PIC16F72 2 FIGURE 9- WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) Receiving Address R SDA SCL S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) 2 FIGURE 9- WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address SDA SCL Data is sampled SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP (SSPCON<4>) DS39597B-page 50 Receiving Data ACK ACK Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full ...
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... SSPIF CCP1IF TMR2IF TMR1IF — — SSPIE CCP1IE TMR2IE TMR1IE 2 C mode) Address Register SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 D R/W PIC16F72 2 C bus Value on Value on Bit 1 Bit 0 all other POR, BOR RESETS 0000 000x 0000 000u INTF RBIF -0-- 0000 0000 0000 ...
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... PIC16F72 NOTES: DS39597B-page 52 2002 Microchip Technology Inc. ...
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... ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The analog-to-digital (A/D) converter module has five inputs for the PIC16F72. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number. The output of the sample and hold is the input into the converter, which generates the result via successive approximation ...
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... PIC16F72 REGISTER 10-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh) U-0 — bit 7 bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 PCFG<2:0>: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x A = Analog input Legend Readable bit - n = Value at POR The ADRES register contains the result of the A/D con- version ...
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... Microchip Technology Inc. CHS2:CHS0 V AIN (Input Voltage 000 or 010 or 100 001 or 011 or 101 PCFG2:PCFG0 V DD Sampling Switch ≤ leakage ± 500 PIC16F72 100 RA5/AN4 011 RA3/AN3/V REF 010 RA2/AN2 001 RA1/AN1 000 RA0/AN0 C HOLD = DAC capacitance = 51 Sampling Switch ( k Ω ) DS39597B-page 55 ...
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... PIC16F72 10.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 10-2. The source impedance (R ) and the internal sampling ...
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... TMR2IE TMR1IE -0-- 0000 CHS2 CHS1 CHS0 GO/DONE — — — — PCFG2 PCFG1 RA5 RA4 RA3 RA2 RA1 PORTA Data Direction Register PIC16F72 Value on Value on Bit 0 all other POR, BOR RESETS RBIF 0000 000x 0000 000u -0-- 0000 -0-- 0000 xxxx xxxx uuuu uuuu ADON ...
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... PIC16F72 NOTES: DS39597B-page 58 2002 Microchip Technology Inc. ...
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... With these two timers on-chip, most applications need no external RESET circuitry. 2002 Microchip Technology Inc. PIC16F72 SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt ...
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... PIC16F72 REGISTER 11-1: CONFIGURATION WORD (ADDRESS 2007h) U-1 U-1 U-1 U-1 U-1 — — — — — bit13 bit 13-7 Unimplemented: Read as ‘1’ bit 6 BOREN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled bit 5 Unimplemented: Read as ‘1’ bit 4 CP: FLASH Program Memory Code Protection bit ...
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... Oscillator Configurations 11.2.1 OSCILLATOR TYPES The PIC16F72 can be operated in four different Oscil- lator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC Resistor/Capacitor 11 ...
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... OSC Recommended values: 11.3 RESET The PIC16F72 differentiates between various kinds of RESET: • Power-on Reset (POR) • MCLR Reset during normal operation • MCLR Reset during SLEEP • WDT Reset (during normal operation) • WDT Wake-up (during SLEEP) • Brown-out Reset (BOR) Some registers are not affected in any RESET condi- tion ...
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... This is a separate oscillator from the RC oscillator of the CLKI pin. 11.4 MCLR PIC16F72 device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family ...
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... If MCLR is kept low long enough, all delays will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16F72 device operating in parallel. Table 11-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 11-6 shows the RESET conditions for all the registers ...
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... MCLR Reset during SLEEP or interrupt wake-up from 0 SLEEP Program STATUS Counter Register 000h 0001 1xxx 000h 000u uuuu 000h 0001 0uuu 000h 0000 1uuu uuu0 0uuu 000h 0001 1uuu ( uuu1 0uuu PIC16F72 Wake-up from SLEEP 1024 T OSC OSC — PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu DS39597B-page 65 ...
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... PIC16F72 TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, Register Brown-out Reset W xxxx xxxx INDF N/A TMR0 xxxx xxxx PCL 0000h STATUS 0001 1xxx FSR xxxx xxxx PORTA --0x 0000 PORTB xxxx xxxx PORTC xxxx xxxx PCLATH ---0 0000 INTCON 0000 000x ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 11-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED NETWORK): CASE MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2002 Microchip Technology Inc PWRT T OST DD T PWRT T OST DD T PWRT T OST PIC16F72 THROUGH THROUGH THROUGH DS39597B-page 67 ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 11.11 Interrupts The PIC16F72 has up to eight sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regard- less of the status of their corresponding mask bit, or the GIE bit ...
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... W, STATUS registers). This will have to be implemented in software, as shown in Example 11-1. For the PIC16F72 device, the register W_TEMP must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., if W_TEMP is defined at 20h in bank 0, it must also be defined at A0h in bank 1) ...
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... PIC16F72 11.13 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip RC oscillator that does not require any external compo- nents. This RC oscillator is separate from the RC oscil- lator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/ CLKO pins of the device has been stopped, for example, by execution of a SLEEP instruction ...
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... SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. PIC16F72 DS39597B-page 71 ...
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... For general information of serial programming, please refer to the In-Circuit Serial Programming™ (ICSP™) Guide (DS30277). For specific details on programming commands and operations for the PIC16F72 devices, please refer to the latest version of the PIC16F72 FLASH Program Memory Programming Specification (DS39588). DS39597B-page 72 ...
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... INSTRUCTION SET SUMMARY Each PIC16F72 instruction is a 14-bit word divided into an OPCODE that specifies the instruction type and one or more operands that further specify the operation of the instruction. The PIC16F72 instruction set summary in Table 12-2 lists byte-oriented, bit-oriented, and lit- eral and control operations ...
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... PIC16F72 TABLE 12-2: PIC16F72 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ f, d Increment f, Skip if 0 ...
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... Operation: Status Affected: Description: BSF Syntax: k Operands: Operation: Status Affected: Description: PIC16F72 AND W with f [ label ] ANDWF f,d 0 ≤ f ≤ 127 d ∈ [0,1] (W) .AND. (f) → (destination) Z AND the W register with register ‘f’. If ‘d’ = ‘0’, the result is stored in the W register. If ‘d’ = ‘1’, the result is stored back in register ‘ ...
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... PIC16F72 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b 0 ≤ f ≤ 127 Operands: 0 ≤ b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ = ‘0’, the next instruction is executed. If bit ‘b’ = ‘1’, then the next instruc- ...
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... If the result is ‘1’, the next instruc- tion is executed. If the result is ‘0’, then a NOP is executed instead, making instruction. CY 2002 Microchip Technology Inc. PIC16F72 GOTO Unconditional Branch Syntax: [ label ] GOTO k 0 ≤ k ≤ 2047 Operands: k → PC<10:0> ...
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... PIC16F72 IORLW Inclusive OR Literal with W Syntax: [ label ] IORLW k 0 ≤ k ≤ 255 Operands: (W) .OR. k → (W) Operation: Status Affected: Z Description: The contents of the W register are OR’d with the eight-bit literal ‘k’. The result is placed in the W register. IORWF Inclusive OR W with f Syntax: ...
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... None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. 2002 Microchip Technology Inc. PIC16F72 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d 0 ≤ f ≤ 127 Operands: d ∈ ...
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... PIC16F72 SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k 0 ≤ k ≤ 255 Operands (W) → (W) Operation: Status Affected: C, DC, Z Description: The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register. SUBWF Subtract W from f Syntax: [ label ] SUBWF f,d 0 ≤ ...
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... Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers pro- vide symbol information that is compatible with the MPLAB IDE memory display. PIC16F72 DS39597B-page 81 ...
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... PIC16F72 13.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for pre- compiled code to be used with the MPLINK object linker ...
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... Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I and separate headers for connection to an LCD module and a keypad. and PIC16F72 PIC16C62X, PIC16C71, PIC16C8X, that supports the ...
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... PIC16F72 13.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple dem- onstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Mod- ule. All the necessary hardware and software is included to run the basic demonstration programs ...
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... DEVELOPMENT TOOLS FROM MICROCHIP MCP2510 MCRFXXX HCSXXX 93CXX 25CXX/ 24CXX/ PIC18FXXX PIC18CXX2 PIC17C7XX PIC17C4X PIC16C9XX PIC16F8XX PIC16F8X PIC16C8X/ PIC16C7XX PIC16C7X PIC16F62X PIC16CXXX PIC16C6X PIC16C5X PIC14000 PIC12CXXX Tools Software Emulators Debugger Programmers 2002 Microchip Technology Inc. PIC16F72 Kits Eval and Boards Demo DS39597B-page 85 ...
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... PIC16F72 NOTES: DS39597B-page 86 2002 Microchip Technology Inc. ...
Page 89
... Exposure to maximum rating conditions for extended periods may affect device reliability. 2002 Microchip Technology Inc. (except V , MCLR. and RA4) ......................................... -0. (Note 2) ..............................................................................................0 to +13.5V )..................................................................................................................... ± ............................................................................................................. ± > ∑ rather than tying the pin directly PIC16F72 + 0.3V ∑ {( ∑( DS39597B-page ...
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... PIC16F72 FIGURE 14-1: PIC16F72 (INDUSTRIAL, EXTENDED) VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V FIGURE 14-2: PIC16LF72 (INDUSTRIAL) VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. (12 MHz/V) (V MAX Note the minimum voltage of the PICmicro DDAPPMIN ...
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... DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) PIC16LF72 (Industrial) PIC16F72 (Industrial, Extended) Param Sym Characteristic No. V Supply Voltage DD D001 PIC16LF72 D001 PIC16F72 D001A D002* V RAM Data Retention DR Voltage (Note 1) D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 Rise Rate to ensure ...
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... PIC16F72 14.1 DC Characteristics: PIC16F72 (Industrial, Extended) PIC16LF72 (Industrial) (Continued) PIC16LF72 (Industrial) PIC16F72 (Industrial, Extended) Param Sym Characteristic No. I Supply Current (Notes D010 PIC16LF72 D010A D010 PIC16F72 D013 ∆I D015* Brown-out Reset Current BOR (Note 6) I Power-down Current (Notes D020 PIC16LF72 D021 ...
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... Note oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input not recommended that the PIC16F72 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. ...
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... Note oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input not recommended that the PIC16F72 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. ...
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... OSC2 for OSC2 output 2002 Microchip Technology Inc specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Load Condition Pin V SS PIC16F72 DS39597B-page 93 ...
Page 96
... PIC16F72 FIGURE 14-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKO TABLE 14-1: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Symbol Characteristic No. F External CLKI Frequency OSC (Note 1) Oscillator Frequency (Note External CLKI Period OSC (Note 1) Oscillator Period (Note Instruction Cycle Time CY (Note 1) 3 TosL, External Clock in (OSC1) ...
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... T + 200 OSC 0 — Standard (F) 100 Extended (LF) 200 0 Standard (F) — Extended (LF) — Standard (F) — Extended (LF) — OSC PIC16F72 New Value Typ† Max Units Conditions 75 200 ns (Note 1) 75 200 ns (Note 1) 35 100 ns (Note 1) 35 100 ns (Note 1) — 0 ...
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... PIC16F72 FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer Reset I/O Pins Note: Refer to Figure 14-3 for load conditions. FIGURE 14-7: BROWN-OUT RESET TIMING V DD ...
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... Standard(F) Greater of: — Extended(LF) Greater of Standard(F) 60 — Extended(LF) 100 — DC — — OSC PIC16F72 48 Max Units Conditions — ns Must also meet parameter 42 — ns — ns Must also meet parameter 42 — ns — ns — prescale value (2, 4, ..., 256) — ns Must also meet parameter 47 — ...
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... PIC16F72 FIGURE 14-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 ) RC2/CCP1 (Capture Mode) RC2/CCP1 (Compare or PWM Mode) Note: Refer to Figure 14-3 for load conditions. TABLE 14-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Param Symbol Characteristic No. 50* TccL CCP1 input low No Prescaler time With Prescaler 51* TccH CCP1 input high ...
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... SPI MASTER MODE TIMING (CKE = 1, SMP = SCK (CKP = SCK (CKP = 1) SDO MSb SDI MSb In 74 Note: Refer to Figure 14-3 for load conditions. 2002 Microchip Technology Inc MSb Bit6 - - - - - -1 75, 76 Bit6 - - - - LSb Bit6 - - - - - -1 75, 76 Bit6 - - - -1 LSb In PIC16F72 79 78 LSb LSb DS39597B-page 99 ...
Page 102
... PIC16F72 FIGURE 14-12: SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) 80 SDO SDI MSb In 73 Note: Refer to Figure 14-3 for load conditions. FIGURE 14-13: SPI SLAVE MODE TIMING (CKE = SCK (CKP = 0) 71 SCK (CKP = 1) MSb SDO SDI SDI ...
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... Microchip Technology Inc. Characteristic Min 100 100 Standard(F) — Extended(LF) — — 10 Standard(F) — Extended(LF) — — Standard(F) — Extended(LF) — — 1 PIC16F72 Typ† Max Units Conditions — — — — — — ns — — ns — — — 50 ...
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... PIC16F72 2 TABLE 14- BUS START/STOP BITS REQUIREMENTS Param Symbol Characteristic No. 90 START condition SU STA Setup time 91 START condition HD STA Hold time 92 STOP condition SU STO Setup time STOP condition HD STO Hold time * These parameters are characterized but not tested. 2 FIGURE 14-15 BUS DATA TIMING ...
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... R SU DAT PIC16F72 Units Conditions µs Device must operate at a minimum of 1.5 MHz µs Device must operate at a minimum of 10 MHz µs Device must operate at a minimum of 1.5 MHz µ ...
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... PIC16F72 TABLE 14-9: A/D CONVERTER CHARACTERISTICS: PIC16F72 (INDUSTRIAL) Param Sym Characteristic No. A01 N Resolution PIC16F72 R PIC16LF72 A02 E Total Absolute Error ABS A03 E Integral Linearity Error IL A04 E Differential Linearity Error DL A05 E Full Scale Error FS A06 E Offset Error OFF A10 — Monotonicity (Note 3) A20 ...
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... Typ† Max Units PIC16F72 1.6 — PIC16LF72 2.0 — PIC16F72 2.0 4.0 PIC16LF72 3.0 6.0 9 — 5* — — — OSC cycle. CY PIC16F72 NEW_DATA DONE Conditions µs ≥ 3.0V — T based, V OSC REF µs — T based, OSC 2.0V ≤ V ≤ 5.5V REF µ ...
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... PIC16F72 NOTES: DS39597B-page 106 2002 Microchip Technology Inc. ...
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... Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) 6 Minimum: mean – 3 (-40°C to +125° 2002 Microchip Technology Inc. vs. F OVER V (HS MODE) OSC DD 3 vs. F OVER V (HS MODE) OSC PIC16F72 5.5 V 5.0 V 4 DS39597B-page 107 ...
Page 110
... PIC16F72 FIGURE 15-3: TYPICAL I DD 0.9 Typical: statistical mean @ 25°C 0.8 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 FIGURE 15-4: MAXIMUM I DD 1.2 Typical: statistical mean @ 25°C 1.0 Maximum: mean + 3 (-40° ...
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... Minimum: mean – 3 (-40°C to +125° 2002 Microchip Technology Inc. vs. F OVER V (LP MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. (kHz) OSC vs. F OVER V (LP MODE) OSC DD 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2. (kHz) OSC PIC16F72 80 90 100 80 90 100 DS39597B-page 109 ...
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... PIC16F72 FIGURE 15-7: AVERAGE F OSC (RC MODE pF 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 FIGURE 15-8: AVERAGE F OSC (RC MODE 100 pF 5.0 4.0 3.0 2.0 1.0 0.0 2.5 3.0 DS39597B-page 110 vs. V FOR VARIOUS VALUES Operation above 4 MHz is not recomended 3 ...
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... Minimum: mean – 3 (-40°C to +125°C) 0.01 2.0 2.5 2002 Microchip Technology Inc. vs. V FOR VARIOUS VALUES 3.5 4.0 V (V) DD Max 125°C Max 85°C Typ 25°C 3.0 3.5 4.0 V (V) DD PIC16F72 4.5 5.0 5.5 4.5 5.0 5.5 DS39597B-page 111 ...
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... PIC16F72 FIGURE 15-11: I vs. V BOR DD 1,000 Max (125˚C) Typ (25˚C) Device in RESET 100 Note: Device current in RESET depends on Oscillator mode, frequency and circuit. Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125° ...
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... V (V) DD OVER TEMPERATURE (- +125 C) DD 3.0 3.5 4.0 V (V) DD PIC16F72 (- +125 C) DD Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) Max Min 4.5 5.0 5.5 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – ...
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... PIC16F72 FIGURE 15-15: TYPICAL, MINIMUM AND MAXIMUM V 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 Typical: statistical mean @ 25°C 1.5 Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.0 0.5 0 FIGURE 15-16: TYPICAL, MINIMUM AND MAXIMUM V 3 ...
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... Minimum: mean – 3 (-40°C to +125°C) 2.0 1.5 1.0 0.5 0 2002 Microchip Technology Inc. vs 5V, - +125 Typ (25°C) Min (-40° (-mA 3V, - +125 Typ (25°C) Min (-40° (-mA) OL PIC16F72 Max (125°C) Max (85° Max (125°C) Max (85° DS39597B-page 115 ...
Page 118
... PIC16F72 FIGURE 15-19: MINIMUM AND MAXIMUM V 1.5 1.4 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to +125°C) Minimum: mean – 3 (-40°C to +125°C) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 2.0 2.5 FIGURE 15-20: MINIMUM AND MAXIMUM V 4.0 Typical: statistical mean @ 25° ...
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... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2002 Microchip Technology Inc. PIC16F72 Example PIC16F72-I/SP 0217017 Example PIC16F72-I/SO 0210017 Example ...
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... PIC16F72 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § ...
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... L .016 .033 .050 .009 .011 .013 B .014 .017 .020 PIC16F72 A2 MILLIMETERS MIN NOM MAX 28 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.32 7.49 7.59 17.65 17.87 18.08 0.25 0.50 ...
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... PIC16F72 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top ...
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... B .009 .011 .014 L .020 .024 .030 R .005 .007 .010 Q .012 .016 .026 CH .009 .017 .024 12 PIC16F72 MILLIMETERS* MIN NOM MAX 28 0.65 BSC 0.85 1.00 0.65 0.80 0.00 0.01 0.05 0.20 REF. 6.00 BSC 5.75 BSC 3.55 3.70 3.85 6 ...
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... PIC16F72 28-Lead Plastic Quad Flat No Leads Package (ML) 6x6 mm Body (QFN) (Continued SOLDER MASK Dimension Limits Pitch Pad Width Pad Length Pad to Solder Mask *Controlling Parameter Drawing No. C04-2114 DS39597B-page 122 B Units INCHES MIN NOM MAX p .026 BSC B .009 .011 .014 L .020 .024 ...
Page 125
... Microchip Technology Inc. PIC16F72 Revision Description PIC16F872 MSSP SSP 2 (SPI Master/Slave) (SPI MHz 20 MHz 10-bit, 5 Channels 8-bit, 5 Channels FLASH 2K FLASH (1,000 E/W cycles) (1000 E/W cycles) 128 bytes 128 bytes 64 bytes None In-Circuit Debugger, — Low Voltage Programming PIC16F72 2 C Slave) DS39597B-page 123 ...
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... PIC16F72 NOTES: DS39597B-page 124 2002 Microchip Technology Inc. ...
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... BF ....................................................................................... 44 Block Diagrams A/D .............................................................................. 55 Analog Input Model ..................................................... 55 Capture Mode Operation ............................................ 38 Compare Mode Operation .......................................... 39 In-Circuit Serial Programming Connections................ 72 Interrupt Logic ............................................................. 68 On-Chip Reset Circuit ................................................. 63 PIC16F72...................................................................... 5 PORTC ....................................................................... 25 PWM ........................................................................... 41 RA3:RA0 and RA5 Port Pins ...................................... 21 RA4/T0CKI Pin............................................................ 21 RB3:RB0 Port Pins ..................................................... 23 RB7:RB4 Port Pins ..................................................... 23 Recommended MCLR Circuit ..................................... 63 2 SSP Mode ...
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... PIC16F72 F FLASH Program Memory Associated Registers .................................................. 28 Operation During Code Protect................................... 28 Reading....................................................................... 28 FSR Register................................................................... I/O Ports .............................................................................. 21 PORTA ........................................................................ 21 PORTB........................................................................ 23 PORTC........................................................................ Associated Registers .................................................. 51 Master Mode ............................................................... 51 Mode Selection ........................................................... 48 Multi-Master Mode ...................................................... 51 SCL and SDA pins ...................................................... 48 Slave Mode ................................................................. 48 ICEPIC In-Circuit Emulator ................................................. 82 ID Locations ........................................................................ 72 In-Circuit Serial Programming (ICSP) ................................. 72 INDF Register ...
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... RC1/T1OSI ................................................................... 6 RC2/CCP1 .................................................................... 6 RC3/SCK/SCL .............................................................. 6 RC4/SDI/SDA ............................................................... 6 RC5/SDO ...................................................................... 6 RC6............................................................................... 6 RC7............................................................................... 6 V ............................................................................... ................................................................................ 6 SS Pinout Descriptions PIC16F72...................................................................... 6 POP .................................................................................... 19 POR. See Power-on Reset PORTA Associated Registers .................................................. 22 Functions .................................................................... 22 2002 Microchip Technology Inc. PIC16F72 PORTA Register ................................................................... 9 PORTB Associated Registers.................................................. 24 Functions .................................................................... 24 Pull-up Enable (RBPU bit) .......................................... 13 RB0/INT Edge Select (INTEDG bit)............................ 13 RB0/INT Pin, External ...
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... PIC16F72 Registers ............................................................................. 36 ADCON0 (A/D Control 0) ............................................ 53 ADCON1 (A/D Control 1) ............................................ 54 CCPCON1 (Capture/Compare/PWM Control 1) ......... 37 Initialization Conditions (table) .................................... 66 INTCON (Interrupt Control) ......................................... 14 OPTION ...................................................................... 13 PCON (Power Control) ............................................... 17 PIE1 (Peripheral Interrupt Enable 1) ........................... 15 PIR1 (Peripheral Interrupt Flag 1) ............................... 16 PMCON1 (Program Memory Control 1) ...................... 27 SSPCON (Sync Serial Port Control) ........................... 45 SSPSTAT (Synchronous Serial Port Status) ...
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... TMR2ON bit ........................................................................ 36 TOUTPS0 bit....................................................................... 36 TOUTPS1 bit....................................................................... 36 TOUTPS2 bit....................................................................... 36 TOUTPS3 bit....................................................................... 36 TRISA Register ............................................................. 10, 21 TRISB Register ............................................................. 10, 23 TRISC Register ............................................................. 10, 25 2002 Microchip Technology Inc. PIC16F72 U UA....................................................................................... 44 Update Address bit, UA ...................................................... 44 W Wake-up from SLEEP................................................... 59, 71 Interrupts .............................................................. 65, 66 MCLR Reset ............................................................... 66 WDT Reset ................................................................. 66 Watchdog Timer (WDT)................................................ 59, 70 Associated Registers ...
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... PIC16F72 NOTES: DS39597B-page 130 2002 Microchip Technology Inc. ...
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... Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2002 Microchip Technology Inc. PIC16F72 Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F72 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this data sheet easy to follow? If not, why? 4 ...
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... Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. XXX Examples: Pattern a) PIC16F72-04I/SO = Industrial Temp., SOIC package, normal b) PIC16LF72-20I/SS = Industrial Temp., SSOP package, extended range DD c) PIC16F72-20I/ML = Industrial Temp., QFN package, normal range DD PIC16F72 V limits limits V limits DD ...
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... Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 05/16/02 2002 Microchip Technology Inc. ...