ICS1893CY-10LFT IDT, Integrated Device Technology Inc, ICS1893CY-10LFT Datasheet - Page 78
ICS1893CY-10LFT
Manufacturer Part Number
ICS1893CY-10LFT
Description
PHYCEIVER LOW PWR 3.3V 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Datasheet
1.ICS1893CY-10LFT.pdf
(143 pages)
Specifications of ICS1893CY-10LFT
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Other names
1893CY-10LFT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS1893CY-10LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
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7.8 Register 6: Auto-Negotiation Expansion Register
7.8.1 IEEE Reserved Bits (bits 6.15:5)
ICS1893CY-10 Rev 1/07
Table 7-13
Auto-Negotiation process.
Note:
Table 7-13. Auto-Negotiation Expansion Register (register 6 [0x06])
† As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
The ISO/IEC specification reserves these bits for future use. When an STA:
•
•
ICS uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the
ICS1893CY-10, an STA must maintain the default value of these bits. Therefore, ICS recommends that an
STA always write the default value of any reserved bits during all management register write operations.
Reserved bits 5.15:5 are Command Override Write (CW) bits. When the Command Register Override bit
(bit 16.15) is logic:
•
•
6.15
6.14
6.13
6.12
6.11
6.10
6.9
6.8
6.7
6.6
6.5
6.4
6.3
6.2
6.1
6.0
Bit
to all Reserved bits.
Reads a reserved bit, the ICS1893CY-10 returns a logic zero.
Writes to a reserved bit, the STA must use the default value specified in this data sheet.
Zero, the ICS1893CY-10 isolates all STA writes to CW bits.
One, an STA can modify the value of these bits
ICS1893CY-10 Data Sheet - Release
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
Parallel detection fault
Link partner Next Page
able
Next Page able
Page received
Link partner
Auto-Negotiation able
For an explanation of acronyms used in
lists the bits for the Auto-Negotiation Expansion Register, which indicates the status of the
Definition
Copyright © 2007, Integrated Device Technology, Inc.
Always 0
Always 0
Always 0
Always 0
Always 0
Always 0
Always 0
Always 0
Always 0
Always 0
Always 0
No Fault
Link partner is not Next
Page able
Local device is not Next
Page able
Next Page not received
Link partner is not
Auto-Negotiation able
When Bit = 0
All rights reserved.
78
Table
7-13, see
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
detected
Link partner is Next Page
able
Local device is Next Page
able
Next Page received
Link partner is
Auto-Negotiation able
Multiple technologies
When Bit = 1
Chapter 1, “Abbreviations and
Chapter 7 Management Register Set
cess
Ac-
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
CW
RO
RO
RO
RO
RO
SF
LH
LH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Acronyms”.
fault
De-
0†
0†
0†
0†
0†
0†
0†
0†
0†
0†
0†
0
0
1
0
0
Hex
0
0
0
4
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