MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 241
MC68HC711KS2MFN4
Manufacturer Part Number
MC68HC711KS2MFN4
Description
32K EPROM - SLOW MODE
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711KS2MFN4.pdf
(290 pages)
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11.4.2 Input/Output Chip Select
M68HC11K Family
MOTOROLA
Address: $005B
The I/O chip select (CSIO) is programmable for a 4-Kbyte size located
at addresses $1000–$1FFF or 8-Kbyte size located at addresses
$0000–$1FFF. The default active-low polarity can be changed to active
high by setting the IOPL bit in CSCTL. Default validity during high E clock
can be changed to address valid time by setting the IOCSA bit in CSCTL.
Clock stretching can be set from zero to three cycles (See
Stretching). CSIO is disabled out of reset.
IOEN — I/O Chip-Select Enable Bit
IOPL — I/O Chip-Select Polarity Select Bit
IOCSA — I/O Chip-Select Address Valid Bit
IOSZ — I/O Chip-Select Size Select Bit
Reset:
Read:
Write:
0 = CSIO is disabled and port H bit 4 is GPIO.
1 = CSIO is enabled and uses port H bit 4.
0 = CSIO active low
1 = CSIO active high
0 = CSIO is valid during E-clock high time.
1 = CSIO is valid during address valid time.
0 = CSIO size is four Kbytes at $1000–$1FFF.
1 = CSIO size is eight Kbytes at $0000–$1FFF.
Figure 11-6. Chip-Select Control Register (CSCTL)
IOEN
Memory Expansion and Chip Selects
Bit 7
0
IOPL
6
0
IOCSA
5
0
IOSZ
4
0
GCSPR
Memory Expansion and Chip Selects
3
0
PCSEN
2
1
PCSZA
11.4.5 Clock
1
0
Technical Data
Chip Selects
PCSZB
Bit 0
0
241
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