PAC-POWR1220AT8-HS-EVN Lattice, PAC-POWR1220AT8-HS-EVN Datasheet - Page 13

• Manufacturer Part Number: PAC-POWR1220AT8-HS-EVN
• Description: Supervisory Circuits Pwr Mgr Hercules Std Development Kit
• Manufacturer: Lattice
• Series: ispPAC®, MachXO, Herculesr

Specifications of PAC-POWR1220AT8-HS-EVN

• Silicon Manufacturer: Lattice Semiconductor
• Kit Application Type: Power Management
• Application Sub Type: Power Manager
• Kit Contents: Preloaded Board, Eval Board, AC Adapter, USB Connector Cable
• Rohs Compliant: Yes
• Main Purpose: Power Management, ORing Controller / Hot Swap Controller
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR1220AT8, LCMXO2280
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Timing for JTAG Operations
Figure 1-3. Erase (User Erase or Erase All) Timing Diagram
Figure 1-4. Programming Timing Diagram
t
t
t
t
t
t
t
t
t
t
f
t
t
t
ISPEN
ISPDIS
HVDIS
HVDIS
CEN
CDIS
SU1
H
CKH
CKL
MAX
CO
PWV
PWP
Symbol
TMS
TCK
State
State
TCK
TMS
VIH
VIH
VIL
VIL
Program enable delay time
Program disable delay time
High voltage discharge time, program
High voltage discharge time, erase
Falling edge of TCK to TDO active
Falling edge of TCK to TDO disable
Setup time
Hold time
TCK clock pulse width, high
TCK clock pulse width, low
Maximum TCK clock frequency
Falling edge of TCK to valid output
Verify pulse width
Programming pulse width
VIH
VIH
VIL
VIL
Update-IR
Update-IR
t
SU1
t
SU1
t
CKH
t
H
Parameter
t
CKH
t
SU1
t
t
GKL
H
Run-Test/Idle (Erase)
t
SU1
t
CKL
Run-Test/Idle (Program)
t
H
t
H
t
SU1
t
PWP
Select-DR Scan
t
CKH
t
t
SU1
H
Conditions
1-13
t
Select-DR Scan
CKH
t
H
t
SU1
ispPAC-POWR1220AT8 Data Sheet
Min.
200
10
30
30
10
20
20
30
20
—
—
—
—
5
t
CKH
t
H
Run-Test/Idle (Discharge)
t
t
SU1
SU1
t
GKL
Typ.
t
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Specified by the Data Sheet
CKH
t
t
H
CKH
Update-IR
t
H
t
SU2
t
SU1
t
CKL
t
SU1
Max.
15
15
25
15
—
—
—
—
—
—
—
—
—
—
t
CKH
t
t
CKH
H
t
H
Units
MHz
ms
µs
µs
µs
µs
ns
ns
µs
ns
ns
ns
ns
ns