ispPAC-POWR607-01NN32I Lattice, ispPAC-POWR607-01NN32I Datasheet - Page 19

• Manufacturer Part Number: ispPAC-POWR607-01NN32I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. I
• Manufacturer: Lattice

Specifications of ispPAC-POWR607-01NN32I

• Number Of Voltages Monitored: 6
• Undervoltage Threshold: 0.8 V
• Output Type: Open Collector / Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Power-up Reset Delay (typ): 300 us
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.64 V
• Supply Current (typ): 3.5 mA
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
In-System Programming
The ispPAC-POWR607 is an in-system programmable device. This is accomplished by integrating all E
tion memory on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG interface at
normal logic levels. Once a device is programmed, all configuration information is stored on-chip, in non-volatile
E
described in the JTAG interface section of this data sheet.
User Electronic Signature
A user electronic signature (UES) feature is included in the E
sists of 32 bits that can be configured by the user to store unique data such as ID codes, revision numbers or inven-
tory control data. The specifics of this feature are discussed in the IEEE 1149.1 serial interface section of this data
sheet.
Electronic Security
An electronic security “fuse” (ESF) bit is provided in every ispPAC-POWR607 device to prevent unauthorized read-
out of the E
user bits in the device. This cell can only be erased by reprogramming the device, so the original configuration can-
not be examined once programmed. Usage of this feature is optional. The specifics of this feature are discussed in
the IEEE 1149.1 serial interface section of this data sheet.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer soft-
ware. Devices can then be ordered through the usual supply channels with the user’s specific configuration already
preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production
programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
Evaluation Fixture
Because the features of an ispPAC-POWR607 are all included in the larger ispPAC-POWR1220AT8 device,
designs implemented in an ispPAC-POWR607 can be verified using an ispPAC-POWR1220AT8 engineering proto-
type board connected to the parallel port of a PC with a Lattice ispDOWNLOAD
proper layout techniques and can be used in real time to check circuit operation as part of the design process.
Input and output connections are provided to aid in the evaluation of the functionality implemented in ispPAC-
POWR607 for a given application. (Figure 4-16).
Figure 4-16. Download from a PC
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispPAC-POWR607 is facilitated via an IEEE 1149.1 test
access port (TAP). It is used by the ispPAC-POWR607 as a serial programming interface. A brief description of the
2
CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPAC-POWR607 instructions are
2
CMOS configuration bit patterns. Once programmed, this cell prevents further access to the functional
PAC-Designer
Software
4-19
ispDOWNLOAD
Cable (6')
2
CMOS memory of the ispPAC-POWR607. This con-
4
ispPAC-POWR
Circuitry
System
1220AT8
Other
Device
ispPAC-POWR607 Data Sheet
®
cable. The board demonstrates
2
configura-