ispPAC-POWR607-01NN32I Lattice, ispPAC-POWR607-01NN32I Datasheet - Page 20

• Manufacturer Part Number: ispPAC-POWR607-01NN32I
• Description: Supervisory Circuits Prec. Prog. Pwr Sppl y Seq. Mon. I
• Manufacturer: Lattice

Specifications of ispPAC-POWR607-01NN32I

• Number Of Voltages Monitored: 6
• Undervoltage Threshold: 0.8 V
• Output Type: Open Collector / Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Power-up Reset Delay (typ): 300 us
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.64 V
• Supply Current (typ): 3.5 mA
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispPAC-POWR607 JTAG interface follows. For complete details of the reference specification, refer to the publica-
tion, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now includes
IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the isp-
PAC-POWR607. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register, which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the configuration register, shifting
data in, and then executing a program configuration instruction, after which the data is transferred to internal
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tions are defined that access all data registers and perform other internal control operations. For compatibility
between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func-
tionally specified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by
the manufacturer. The two required registers are the bypass and boundary-scan registers. Figure 4-17 shows how
the instruction and various data registers are organized in an ispPAC-POWR607.
Figure 4-17. ispPAC-POWR607 TAP Registers
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 4-18. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
Test/Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register and Pause-Instruction-Register. But
there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a
reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on
default state.
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CMOS cells. It is these non-volatile cells that store the configuration or the ispPAC-POWR607. A set of instruc-
TDI
TEST ACCESS PORT (TAP)
INSTRUCTION REGISTER (8 BITS)
ADDRESS REGISTER (61 BITS)
TCK
IDCODE REGISTER (32 BITS)
BYPASS REGISTER (1 BIT)
DATA REGISTER (81 BITS)
UES REGISTER (32 BITS)
LOGIC
TMS
4-20
OUTPUT
LATCH
TDO
ispPAC-POWR607 Data Sheet
NON-VOLATILE
MEMORY
E
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CMOS