MC145572PB Freescale Semiconductor, MC145572PB Datasheet

no-image

MC145572PB

Manufacturer Part Number
MC145572PB
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC145572PB

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC145572PB
Manufacturer:
FREESCAL
Quantity:
4 000
Part Number:
MC145572PB
Manufacturer:
MOTOLOLA
Quantity:
885
Part Number:
MC145572PB
Manufacturer:
FREESCALE
Quantity:
896
Part Number:
MC145572PB
Manufacturer:
ST
Quantity:
550
Part Number:
MC145572PB
Manufacturer:
TI
Quantity:
8
Part Number:
MC145572PB
Manufacturer:
FREESCALE
Quantity:
896
Part Number:
MC145572PB
Manufacturer:
MOT
Quantity:
1 000
Part Number:
MC145572PB
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
MCU Mode Maintenance Channel Operation
MCU Mode Register Description Reference
MCU Mode Activation and Deactivation
MCU Mode Programming Suggestions
Freescale Semiconductor, Inc.
ISDN Basic Access System Overview
For More Information On This Product,
MCU Mode Device Functionality
GCI Mode Functional Description
Go to: www.freescale.com
Electrical Specifications
Pin Descriptions
Mechanical Data
Introduction
Appendices
A–J
10
11
1
2
3
4
5
6
7
8
9

Related parts for MC145572PB

MC145572PB Summary of contents

Page 1

... Freescale Semiconductor, Inc. ISDN Basic Access System Overview MCU Mode Register Description Reference MCU Mode Device Functionality MCU Mode Activation and Deactivation MCU Mode Maintenance Channel Operation GCI Mode Functional Description MCU Mode Programming Suggestions For More Information On This Product, Go to: www.freescale.com ...

Page 2

... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

Page 3

... Freescale Semiconductor, Inc. MC145572 ISDN U-Interface Transceiver All brand and product names appearing in this document are registered trademarks of their respective holders. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

Page 4

... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

Page 5

... Freescale Semiconductor, Inc. TABLE OF CONTENTS 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 SUPPLEMENTAL DOCUMENTATION 1.3 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 6

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (continued) 4.4.7 BR6: Loopback Control Register 4.4.8 BR7: IDL2 Configuration Register 4.4.9 BR8: Transmit Framer and Mode Control Register 4.4.10 BR9: Maintenance Channel Configuration Register 4.4.11 BR10: Overlay Select Register 4.4.12 BR11: Activation State Register 4.4.13 BR12: Activation State Test Register 4 ...

Page 7

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (continued) 5.6 LOOPBACKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 8

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (continued) GCI MODE FUNCTIONAL DESCRIPTION 8.1 FUNCTIONAL OVERVIEW 8.2 INTERFACE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 9

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (continued) 10.10 SUPERFRAME TRANSMIT AND RECEIVE (SFAX/SFAR) TIMING 10.10.1 SFAX Input Timing in IDL2 (Master or Slave) Short Frame Mode 10.10.2 SFAX Input Timing in IDL2 (Master or Slave) Long Frame Mode 10.10.3 SFAX/SFAR Output Timing in IDL2 (Master or Slave) Short Frame Mode 10 ...

Page 10

... Freescale Semiconductor, Inc. TABLE OF CONTENTS (concluded) PRINTED CIRCUIT BOARD LAYOUT C.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 11

... Freescale Semiconductor, Inc. Figure Title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 12

... Freescale Semiconductor, Inc. LIST OF FIGURES (Continued) Figure Title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 13

... Figure 11–1. MC145572FN Pin Assignment Figure 11–2. MC145572PB Pin Assignment Figure 11–3. MC145572FN Mechanical Outline Figure 11–4. MC145572PB Mechanical Outline Figure A–1. Motorola Silicon Applications and the MC145572EVK Figure A–2. MC145572EVK Functional Block Diagram Figure B–1. Schematic Reference for U–Interface Transformer Figure C– ...

Page 14

... Freescale Semiconductor, Inc. Table Title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 15

... Freescale Semiconductor, Inc. 1.1 INTRODUCTION The MC145572 U–interface transceiver is a single chip device for the Integrated Services Digital Net- work Basic Access Interface that conforms to the American National Standard ANSI T1.601–1992. The device, which can be configured for LT (Line Termination (Network Termination) applica- tions, performs all necessary Layer 1 functions while utilizing 2B1Q line coding. The MC145572 is a redesign of the MC145472 and MC14LC5472 U– ...

Page 16

... Freescale Semiconductor, Inc. Appendix G, Performance , shows graphs of typical line interface circuit performance. Appendix H, Test and Debug, gives test and debug information on high impedance digital output mode, control of transmit signals, and characterization of the pullable crystal. Appendix I, Glossary of Terms and Abbreviations, contains terms found in this and other Motorola publications concerned with Motorola Semiconductor Products for Communications ...

Page 17

... Freescale Semiconductor, Inc. Sections, continued: 3.3.2 MCU/GCI: 3.3.2 PAR/SER: 3.3.4 TxBCLK: 3.3.4 RxBCLK: 3.3.4 SFAR: 3.3.4 SFAX: 3.3.4 S0: 3.3.6 FREQREF: LT Mode 3.3.6 FREQREF: NT Mode 4.5.6 OR5 5.6.3 Pseudo Code modified 5.6.4 Added new section on Superframe Framer–to–Deframer loopbacks in systems having multiple MC145572s 5 ...

Page 18

... Freescale Semiconductor, Inc. For More Information On This Product, 1–4 MC145572 Go to: www.freescale.com MOTOROLA ...

Page 19

... Freescale Semiconductor, Inc. ISDN BASIC ACCESS SYSTEM OVERVIEW 2.1 ISDN REFERENCE MODEL The ISDN reference model is shown in Figure 2–1. This is a general model that can be adapted to many different implementations of the ISDN. The diagram indicates the position of the U–reference point between the LT and the Network Termination 1 (NT1) blocks in the model. ...

Page 20

... Freescale Semiconductor, Inc. TA MC145488 MC145574 SCP S/T DDLC CHIP IDL MC14LC5480 MPU CODEC SYSTEM HOST BUS TE1 MC68302 MC145574 SCP S/T IMP CHIP IDL MC14LC5480 RAM CODEC ROM Figure 2–2. MC145572 Typical ISDN Applications The NT1 converts the 2–wire U–interface to the 4–wire S/T–interface as shown. By combining an MC145572 with a Motorola MC145574 S/T– ...

Page 21

... Freescale Semiconductor, Inc. 2.3 NON-ISDN U-INTERFACE TRANSCEIVER APPLICATIONS Typical non–ISDN pair gain application block diagrams are shown in Figures 2–3 and 2–4. Pair gain is a technique to multiplex two or more analog phone lines over a single twisted pair. ANALOG LINE 1 TO CENTRAL OFFICE ...

Page 22

... Freescale Semiconductor, Inc. For More Information On This Product, 2–4 MC145572 Go to: www.freescale.com MOTOROLA ...

Page 23

... Freescale Semiconductor, Inc. 3.1 INTRODUCTION This chapter describes the MC145572 pins and their operation. Additionally, quick reference tables are provided. These tables are organized by the three major modes of operation and by package type. 3.2 PIN DESCRIPTION QUICK REFERENCE The following tables (Tables 3–1 through 3–5) list the MC145572 pins in functional groups and provide brief pin descriptions ...

Page 24

... Freescale Semiconductor, Inc. Table 3–1. Power Supply and Mode Selection Pins (See Sections 3.3.1 and 3.3.2) Pin No. Pin Name TQFP PLCC 23, 36 CAP3V 28 1 RESET 41 14 NT/ MCU/GCI 26 43 PAR/SER 40 13 Table 3–2. Time Division Multiplex Interface Pins (See Section 3.3.3) Pin No ...

Page 25

... Freescale Semiconductor, Inc. Table 3–3. Digital Data Interface Pins (See Section 3.3.4) Pin Name MCU/ MCU/PCP GCI SCP Mode Mode Mode TQFP SCPEN CS IN1 4 SCPCLK R/W IN2 3 SCPRx D0 OUT1 1 SCPTx D1 OUT2 2 IRQ IRQ — 44 4.096 D2 4.096 17 CLKOUT CLKOUT 15.36 D3 15.36 18 CLKOUT ...

Page 26

... Freescale Semiconductor, Inc. Pin Name TQFP TxP, TxN 36, 39 RxP, RxN 32 ref P, V ref N 35, 34 Table 3–5. Phase Locked Loop and Clock Pins (See Section 3.3.6) Pin Name TQFP FREQREF 25 XTAL in , XTAL out 16, 15 3.3 PIN DESCRIPTIONS The following descriptions are divided into the same functional groups as the Pin Description Quick Reference Tables in Section 3.2 and provide more information about the particular subsystem of the device and the associated pins. Refer to Figures 11– ...

Page 27

... Freescale Semiconductor, Inc Rx Tx: Negative Analog Power Supply Two of the six negative power supply pins are and V DD Rx, and they should be con- nected to ground. These pins provide a ground reference to the analog receive and transmit subsystems of the device, and each should be decoupled with separate 0.1 F ceramic capacitors and V DD Tx, respectively ...

Page 28

... Freescale Semiconductor, Inc. MCU/GCI: MCU/GCI Select Input A logic 1 applied to this pin selects the MCU mode. This requires an external MCU to access the internal control/status register of the MC145572. 2B+D data only is transferred over the time division multiplex bus. In MCU mode, four data formats are available on the IDL2 interface. ...

Page 29

... Freescale Semiconductor, Inc. and is rising edge aligned with the rising edge of the DCL signal. This pin is an input when the TDM interface is in Slave mode and an output in the Master mode as established by the M/S pin. See Figures 5–17 through 5–20. When the MC145572 mode and M this output is phase locked to the signal received at the U– ...

Page 30

... Freescale Semiconductor, Inc. adding or subtracting a single 20.48 MHz clock period during the high time of DCL. Since this occurs during two consecutive 8 kHz frames, the total adjustment is basic frame. See Chapter 10, Electrical Specifications, for the locations of the timing adjust- ment. D out : Data Transmit Output This pin is the output for the data received at the U– ...

Page 31

... Freescale Semiconductor, Inc. SCPRx/D0/OUT1 SCPRx: Serial Control Port Receive Input SCPRx is used to input control, status, and M channel data information to the U–interface transceiver. Data is shifted into the MC145572 on rising edges of SCPCLK. SCPRx is ignored when data is being shifted out of SCPTx or when SCPEN is high. ...

Page 32

... Freescale Semiconductor, Inc. D3: Data 3 In Parallel Control Port mode, this pin functions as bit 3 of the data bus. BUFXTAL/D4 BUFXTAL: Buffered Crystal Output BUFXTAL is the buffered square wave output from the 20.48 MHz oscillator. After reset, this signal is active. This output can be set to a high impedance state by setting OR9(b2 ...

Page 33

... Freescale Semiconductor, Inc. DCH Channel Data In DCH in is the D channel port serial input enabled by setting D channel port enable in Init Group register OR8(b0). D6: Data 6 In Parallel Control Port mode, this pin functions as bit 6 of the data bus. FREF out : GCI Mode Locked Frequency Output In full GCI mode, operating as a slave, this pin provides 2 ...

Page 34

... Freescale Semiconductor, Inc. TxSFS/SFAX/S0 TxSFS: Transmit Superframe Sync Output This output pulses high, 8 bauds prior to the transmit sync word separating the first and second transmitted basic frames in a superframe. Control bits BR14(b0) and BR15A(b3) must both be set enable this pin. The TxSFS output is coincident with the Tx Baud Clock ...

Page 35

... Freescale Semiconductor, Inc. ANSI T1.601–1992 requirements. Some ANSI and ETSI applications require a 32 ppm reference. NT Mode: In MCU/GCI = 1 mode, FREQREF can be enabled as an output when the MC145572 is configured for NT mode by setting OR8(b4 This signal outputs the internally–generated DCL clock when enabled. Its frequency is programmed by the DCL frequency bits BR7(b2) and OR7(b4) ...

Page 36

... Freescale Semiconductor, Inc. at all times. This means that the BUFXTAL out pin can not be used as a master clock source in applica- tions that require a synchronized clock mode, the U–interface transceiver can lock to 80 kbaud 32 ppm receive signals. A single 20.48 MHz pullable crystal must be connected between XTAL in and XTAL out pins of the MC145572 ...

Page 37

... Freescale Semiconductor, Inc. MCU MODE REGISTER DESCRIPTION REFERENCE 4.1 INTRODUCTION This chapter describes all of the MC145572 U–interface transceiver control and status registers avail- able via the Serial and Parallel Control Ports. Tables 4–1 through 4–3 contain Register Maps and Section 4.2.1 contains a Register Index. See Section 4.3 for detailed descriptions of each register. ...

Page 38

... Freescale Semiconductor, Inc. Table 4–2. Byte Register Map (BR0 – BR15A BR0 M40 M41 BR1 M40 M41 BR2 M50 M60 BR3 M50 M60 BR4 febe febe Counter 7 Counter 6 BR5 nebe nebe Counter 7 Counter 6 BR6 U–Loop U–Loop B1 B2 BR7 BR15A OUT2 Select ...

Page 39

... Freescale Semiconductor, Inc. Table 4–3. Overlay Register Map (OR0 – OR13) INIT GROUP REGISTER OVERLAY REGISTERS OR0 – OR9, OR11, AND OR12 b7 b6 OR0 OR1 OR2 OR3 OR4 OR5 OR6 TSA B1 TSA B2 Enable Enable OR7 Internal Line Connect Analog D Channel Loopback ...

Page 40

... Freescale Semiconductor, Inc. Activation (continued) Step Activation State — BR12(b4) Superframe Sync — NR1(b1) Superframe Update Disable — NR2(b1) Timer Disable — BR11(b0) Timer Expire — BR11(b0) Transparent — NR1(b0) Verified act — BR3(b2), BR9(b5:b4) Verified dea — BR3(b1), BR9(b5:b4) Deactivation Request — ...

Page 41

... Freescale Semiconductor, Inc. 4.2.2 Bit Description Legend Each bit described in the following sections has a read/write indicator associated with it. This indicator, shown in the lower right corner of each bit, shows what type of bit resides there. The options are described in Table 4–4. Indicator Type ...

Page 42

... Freescale Semiconductor, Inc. 2. The external microcontroller sets the Activation Request bit, (NR2(b3)). 3. This bit is reset to 0. When this bit is 0, the U–interface transceiver is not permitted to enter power–down mode. The U– interface transceiver has warm start capability regardless of the state of this bit. ...

Page 43

... Freescale Semiconductor, Inc. Error Indication This bit is set to 1 when a timer expires. Time–out sources are: 1. 15–second Activation Timer (BR11(b0)). 2. 480–ms loss of frame/signal. 3. Failure to get NT1 response to the TL signal (10 ms following the cessation of TL). ( duration.) Error Indication is always automatically reset prior to the next IRQ3. This is the result of either setting the Activate Request bit in NR2(b3) or receiving a wakeup tone ...

Page 44

... Freescale Semiconductor, Inc. 4.3.3 NR2: Activation Control Register Register NR2 contains activation/deactivation control bits. All bits are cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). NR2 normally is not written to in GCI mode; if necessary, NR2 can be written to, but bits b3 and b2 should always be written as 0 while the device is in GCI mode. ...

Page 45

... Freescale Semiconductor, Inc. 4.3.4 NR3: Interrupt Status Register This is the interrupt status register, and it is read–only. All bits are cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). Each interrupt status bit in the register operates the same and its corresponding interrupt enable Register NR4, the IRQ pin on the chip will become active. ...

Page 46

... Freescale Semiconductor, Inc. 4.3.6 NR5: IDL2 Data Control Register This register contains controls for the IDL2 interface. More IDL2 controls are in Registers BR6, BR7, and OR0 – OR9. All bits are cleared on Software Reset (NR0(b3)) or Hardware Reset (RESET). See Figures 4–4 and NO TAG in Register BR6 description for clarification regarding the precedence of the swap and blocking functions listed in this register ...

Page 47

... Freescale Semiconductor, Inc. Table 4–5. Register Bit Locations Within the Superframe LT Framing QUAT Positions 1 – 9 Bit Positions 1 – 18 Basic Frame # Sync Word 1 ISW act = start up bit, set = 0 during start up aib = alarm indication bit (set = 0 to indicate interruption) crc = cyclic redundancy check: covers ...

Page 48

... Freescale Semiconductor, Inc. 4.4 BYTE REGISTERS 4.4.1 BR0: M4 Transmit Data Register This register contains the M4 bits that are framed and sent by the Superframe Framer. The bits written to this register are sent out on the next transmit superframe boundary, if Superframe Update Disable (NR2(b1)) is set to 0. This register is double buffered. All bits are set to 1s following a Hard- ware Reset (RESET) or Software Reset (NR0(b3)) ...

Page 49

... Freescale Semiconductor, Inc. 4.4.3 BR2: M5/M6 Transmit Data Register This register contains the reserved M5 and M6 bits that are sent by the Superframe Framer. The bits written to the register are sent out on the next transmit superframe boundary, if Superframe Update Disable (NR2(b1)) is set to 0. All bits are set to 1s following a Hardware Reset (RESET) or Software Reset (NR0(b3)). See BR9(b1) for details concerning use of the far– ...

Page 50

... Freescale Semiconductor, Inc for two consecutive superframes. This bit is updated at the end of the first frame of each super- frame and is provided in this register for status only. See BR9(b5:b4) for more information regarding this bit. When OR7(b0) is set, the M4 act and dea bits must be valid for three superframes before Verified act or Verified dea are updated ...

Page 51

... Freescale Semiconductor, Inc. OR7(b1) is cleared, BR5 counts to $FF and does not roll over. This is the default configuration after any reset to maintain MC145472 compatibility. b7 BR5 nebe Counter 7 rw 4.4.7 BR6: Loopback Control Register This register contains the loopback controls. For normal (no loopback) operation, bits b7:b5 and b3:b1 of BR6 should be 0 ...

Page 52

... Freescale Semiconductor, Inc. Figures 4–1 and 4–2 may be used to determine the combined effect of setting more than one loopback control in BR6, as well as the bits in NR5 and BR7. Only details for the B1 channel are shown, but a similar set of logic applies to both the B2 and D channels. D out and D in refer to the two external pins on the device. There are two control signals shown in Figure 4– ...

Page 53

... Freescale Semiconductor, Inc. U-LOOP TRANSPARENT U-LOOP B1 U-LOOP 2B+D B1 FROM THE U-INTERFACE THE U-INTERFACE a a/b SWAP B1/B2 IDL2-LOOP B1 U-LOOP B1 IDL2-LOOP 2B+D U-LOOP 2B SWAP B1/B2 Figure 4–2. IDL2 Interface Loopback Logic Diagram 4.4.8 BR7: IDL2 Configuration Register This register contains IDL2 interface mode information. BR7 is cleared on Hardware Reset (RESET) or Software Reset (NR0(b3)) ...

Page 54

... Freescale Semiconductor, Inc. GCI IN1/OUT1 This is a read–only/write–only bit. The write only portion, OUT1, is cleared by hardware and software resets. In full GCI mode, entered by holding the pin MCU/GCI low, the state of OUT1 is driven onto a GCI mode dedicated output pin. When read (again, provided the MC145572 is in full GCI mode), bit IN1 reflects the state of a GCI mode dedicated input pin ...

Page 55

... Freescale Semiconductor, Inc. FSR FSX DCL D b11 b12 b13 in D out b11 b12 b13 Figure 4–3. IDL2 Interface Timing in 8–Bit Master Mode FSR FSX DCL D b11 b12 b13 in D out b11 b12 b13 Figure 4–4. IDL2 Interface Timing in 10–Bit Master Mode ...

Page 56

... Freescale Semiconductor, Inc. 4.4.9 BR8: Transmit Framer and Mode Control Register This register contains controls used for test operations such as external loopbacks, Superframe Fram- er Control and State information, and NT/LT mode control. All write capable bits are cleared on a Software Reset (NR0(b3)) or Hardware Reset (RESET). Bits b7 – b4 and b0, are read–only/write–only. ...

Page 57

... Freescale Semiconductor, Inc. transmits the crc and this bit is set, the transmitted crc is inverted. This bit can be cleared or set at any time during transmission of a superframe. This bit functions the same as in the MC145472/ MC14LC5472 after a Hardware Reset (RESET). When OR7(b2) is set to 1, the operation of this bit is modified so that the outgoing crc is only corrupted on the current superframe ...

Page 58

... Freescale Semiconductor, Inc. eoc Trinal–Check Mode (b7 1,0) The eoc Trinal–Check operation checks for three identical consecutive eoc messages being received before loading the eoc message into R6. Register R6 is always updated with the received message when the third identical consecutive message is received. ...

Page 59

... Freescale Semiconductor, Inc. BR9 M4 Control 1:0 OR7 Dual Consecutive Modes (b5 0,0 or 0,1) The M4 Dual Consecutive modes perform a simple algorithm on the received M4 bits, and only interrupt the external microcontroller when an M4 bit has changed state and has remained in the new state for two consecutive superframes. The M4 bit values read from BR1 in this mode are only the most recent values that have been the same for two consecutive superframes. Referring to Table 4– ...

Page 60

... Freescale Semiconductor, Inc. M4 Delta Mode (b5 1,0) The Delta mode compares the M4 data from the previous superframe against the current received superframe M4 data. If there is a difference in at least one bit, BR1 is updated and an IRQ1 interrupt is issued. Note that in this mode, BR1 always contains a copy of the latest received M4 byte from the previous superframe ...

Page 61

... Freescale Semiconductor, Inc. Select Dump Access This bit hides the normal byte register BR13, and the register becomes a byte–wide access port, OR13, to the dump/restore mechanism of the U–chip. Two more bits in the overlay registers control the operat- ing mode of the dump/restore mechanism. See Overlay register OR8. This bit is reset by hardware reset only ...

Page 62

... Freescale Semiconductor, Inc. Activation Timer Disable When this write–only bit is 0, the activation timer operates normally. During activation the timer will time for approximately 15 seconds, and then the Activation Timer Expire bit will become 1, and the activation state machine will react to the time–out. When this bit is set to 1, the activation timer is disabled and the Activation Timer Expire will always read back as 0 ...

Page 63

... Freescale Semiconductor, Inc. Hold Activation State When this bit is set to 1, the activation controller is held in the current state until either a Load Activation State (b5 Step Activation State (b4) is performed. Big Jump Select When this bit is 1, timing phase jumps will be made in four–unit increments. When this bit is 0, timing phase jumps will be made in one– ...

Page 64

... Freescale Semiconductor, Inc. Fast DFE/ARC Beta This bit controls the betas for the DFE and ARC. When set to 1, the DFE and ARC adapt at their highest rate. Clear All Coefficients When set to 1, the coefficients in the DFE, ARC, TEC, and MEC are cleared and the elastic buffer is reset ...

Page 65

... Freescale Semiconductor, Inc. 4.4.16 BR15: Revision Number Register This read–only register contains the revision number of the particular U–interface transceiver device. BR15 is accessed by a SCP or PCP transfer when BR7(b7 and the byte address is 15. b7 BR15 Mask 7 ro Mask 7:0 These bits allow for an electronic determination of the revision number of the MC145572 U–interface transceiver manufacturing mask set ...

Page 66

... Freescale Semiconductor, Inc. 4.5 OVERLAY REGISTERS Table 4–3 shows the registers on MC145572 that overlay the standard byte registers. The SCP address for the overlay registers is the same as the address for the standard byte register set. The overlay registers are substituted for the standard registers, when at least one of BR7(b7) or BR10(b2, b1, b0) is set to 1 ...

Page 67

... Freescale Semiconductor, Inc. 4.5.4 OR3 Timeslot Register Programmed the same way as OR0. This register controls when the B1 timeslot is input from the D in pin. After a hardware or software reset, all bits default maintain MC145472/MC14LC5472 compatibility. b7 OR3 4.5.5 OR4 Timeslot Register Programmed the same way as OR0. This register controls when the B2 timeslot is input from the D in pin ...

Page 68

... Freescale Semiconductor, Inc. TSA B1 Enable This bit is used to enable the B1 channel in IDL2 Timeslot mode. The B1 timeslot is defined through Overlay registers OR0 and OR3. Whenever any channel (B1, B2 enabled for Timeslot mode, all channels enter Timeslot mode Timeslot mode and TSA B1 Enable is 0, then the B1 channel is not present on the pin D out , and the B1 channel transmit on the U– ...

Page 69

... Freescale Semiconductor, Inc. Internal Analog Loopback When this bit is set to 1, the analog loopback path is inside the MC145572. Default after any reset external analog loopback path. Line Connect When this bit is 1, the U–interface line can remain connected during analog loopbacks. When this bit is 0, the line must be disconnected ...

Page 70

... When this bit is set invokes a receive analog loopback on the MC145572. CLKOUT 2048 When this bit is set enables a 20.48 MHz buffered clock output on pin 25 of the MC145572FN and on pin 8 of the MC145572PB. 4096 Hirate When this bit is set causes the 4.096 MHz clock output to cleanly transition to a 10.24 MHz rate ...

Page 71

... Freescale Semiconductor, Inc. 2048 Disable When this bit is set causes the 20.48 MHz clock output at BUFXTAL high impedance. 1536 Disable When this bit is set causes the 15.36 CLKOUT pin to go high impedance. 4096 Disable When this bit is set causes the 4.096 CLKOUT pin to go high impedance. This bit may only be written to once, following a hardware or software reset. Once the 4.096 CLKOUT pin has been turned off by setting this bit, it can only be re– ...

Page 72

... Freescale Semiconductor, Inc. For More Information On This Product, 4–36 MC145572 Go to: www.freescale.com MOTOROLA ...

Page 73

... Freescale Semiconductor, Inc. MCU MODE DEVICE FUNCTIONALITY 5.1 FUNCTIONAL OVERVIEW This chapter describes the operation of MC145572 when operated in the MCU mode. A functional block diagram of the MC145572 U–interface transceiver is shown in Figure 5–1. This device utilizes mixed analog and digital signal processing circuit technology to implement an adaptively equalized echo cancelling full– ...

Page 74

... Freescale Semiconductor, Inc. is converted to a digital word in the – (sigma–delta) ADC (analog–to–digital converter). After filter- ing, an adaptively generated replica of the transmitted signal, calculated by the echo canceller, is sub- tracted from the combined signal leaving only the far–end signal. In addition, phase distortion present in the far– ...

Page 75

... Freescale Semiconductor, Inc. Table 5–1. Mode Pin Breakout Summary and Comparison PLCC Pin No. Function I/O 24 I/O 23 TxP/TxN 9, 12 RxP/RxN ref ref XTAL in / XTAL out 33, 32 FREQREF 42 RESET 14 MCU/GCI 43 NT/LT 15 M/S 16 PAR/SER 13 For More Information On This Product, MOTOROLA TQFP Pin No. MC145572 29, 5 Connect to Ground ...

Page 76

... Freescale Semiconductor, Inc. Table 5–2. Pin Function per Mode and MC14LC5472 Comparison PLCC TQFP MCU/SCP Pin No. Pin No. Mode SCPEN 20 3 SCPCLK 18 1 SCPRx 19 2 SCPTx 27 10 FSR (Note FSX (Note 4.096 CLKOUT 35 18 15.36 CLKOUT 38 21 BUFXTAL 26 9 TxSFS (Note 5) 25 ...

Page 77

... Freescale Semiconductor, Inc. 5.3.1 SCP Mode The MC145572 is equipped with an industry standard SCP interface. The SCP is used by an external controller, such as an M68HC05 family microcontroller, MC145488 Dual Data Link Controller, or MC68302 Integrated Multiprotocol Processor, to communicate with the U–interface transceiver. The SCP is a full–duplex four–wire interface with control and status information passed to and from the U– ...

Page 78

... Freescale Semiconductor, Inc. 5.3.1.1 NIBBLE REGISTER OPERATION The 4–bit nibble registers are accessed via an 8–bit SCP interface operation, as shown in Figure 5–3 for a write operation and Figure 5–4 for a read operation. The first bit of the transfer on SCPRx is a read/write (R/W) bit, indicating the purpose of the operation. This is followed by a 3–bit address field (A2:A0), which specifies nibble address 0 through nibble address 5. (Nibble addresses 6 and 7 have other purposes, which are described later.) For a write operation, the 4– ...

Page 79

... Freescale Semiconductor, Inc. 5.3.1.2 REGISTER R6 OPERATION The 12–bit Nibble register 6 is located at nibble register address 6 and can be accessed with two sequential 8–bit SCP interface operations, as shown in Figures 5–5 and 5–6. In this case, the second 8–bit operation accesses the last 8 data bits (D7:D0) as shown. Alternatively, this register can be ac- cessed with a single 16– ...

Page 80

... Freescale Semiconductor, Inc. SCPEN SCPCLK SCPRx R/W A2 SCPTx Figure 5–7. SCP eoc Register R6 Write Operation Using Single 16 SCPEN SCPCLK SCPRx R/W A2 SCPTx HIGH IMPEDANCE Figure 5–8. SCP eoc Register R6 Read Operation Using Single 16 For More Information On This Product, 5– D11 D10 ...

Page 81

... Freescale Semiconductor, Inc. 5.3.1.3 BYTE REGISTER OPERATION The 16 byte registers are addressed by addressing nibble address 7 followed by a 4–bit byte register address (A3:A0), as shown in Figures 5–9 and 5–10. A second 8–bit operation transfers the data word (D7:D0). Alternatively, these registers can be accessed with a single 16–bit operation, as shown in Figures 5– ...

Page 82

... Freescale Semiconductor, Inc. SCPEN SCPCLK SCPRx R/W SCPTx Figure 5–11. SCP Byte Register Write Operation Using Single 16 SCPEN SCPCLK SCPRx R/W SCPTx HIGH IMPEDANCE Figure 5–12. SCP Byte Register Read Operation Using Single 16 For More Information On This Product, 5– HIGH IMPEDANCE ...

Page 83

... Freescale Semiconductor, Inc. 5.3.2 PCP Mode In PCP mode, the MC145572 is configured to have a single address byte wide data port for access to the internal register set. A read/write pin (R/W) and chip select pin (CS) are provided to enable read or write accesses to the data port. For an external microcontroller, such as the MC68302, to access an individual nibble, byte, or overlay register ...

Page 84

... Freescale Semiconductor, Inc. 5.3.2.1 PCP NIBBLE REGISTER OPERATION Data is written to a nibble register using a single PCP write operation. The 8–bit data word must contain the register address, write bit cleared to 0, and the data to be written as shown in Figure 5–14. Data is read from a nibble register by first writing the nibble register address with the read indicator bit set the parallel data port. Next, the parallel data port is read and data from the register pointed to by the previous write operation appears on bits 0 through 3 of the port. See Figure 5– ...

Page 85

... Freescale Semiconductor, Inc. 5.3.2.2 PCP REGISTER R6 OPERATION Data is written to Register R6, the eoc register, by writing two successive bytes to the PCP. The first byte must contain the register address, write bit cleared to 0, and the most significant four bits of data to be written, as shown in Figure 5–15. ...

Page 86

... Freescale Semiconductor, Inc. 5.3.2.3 PCP BYTE REGISTER OPERATION Data is written to a byte register by writing two successive bytes to the PCP. The first byte must contain the register address, write bit cleared to 0, and the address of the byte register. The second byte contains the actual data to be written to the selected byte register (see Figure 5–16). ...

Page 87

... Freescale Semiconductor, Inc. 5.4 IDL2 TIME DIVISION BUS INTERFACE The IDL2 interface consists of six pins: M/S, FSX, FSR, DCL and D out . With the M/S pin, the IDL2 interface can be configured as a timing master (FSR, FSX, and DCL are outputs timing slave (FSR, FSX, and DCL are inputs). The master or slave configuration is independent mode selection. The IDL2 interface receives 2B+D data on the D in pin and buffers it through a FIFO to the U– ...

Page 88

... Freescale Semiconductor, Inc. 5.4.1 Short Frame Operation Short frame operation is the same as the IDL interface used on the MC145472 and MC14LC5472 U–interface transceivers with one exception. The MC145572 provides for two 8 kHz frame sync pins, FSX and FSR, when operated in IDL2 mode. The FSX pin is used to indicate IDL2 frame synchro- nization for data input into the D in pin for transmission onto the U– ...

Page 89

... Freescale Semiconductor, Inc. DCL FSR Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç out FSX Ç Ç Ç Ç Ç Ç Ç Ç Ç ...

Page 90

... Freescale Semiconductor, Inc. 5.4.2 Long Frame Operation When configured for long frame mode, the 8 kHz frame sync is active during the data transfer. The FSX pin is used to indicate frame synchronization for data input into the D in pin for transmission onto the U–interface. The FSR pin is used to indicate frame synchronization for data recovered from the U– ...

Page 91

... Freescale Semiconductor, Inc. DCL FSR out FSX Ç Ç Ç Ç Ç Ç DCL FSR out FSX Ç Ç Ç Ç Ç Ç Ç Ç DON'T CARE Ç Ç Ç Ç Ç Ç Ç Ç Figure 5–22. IDL2 Interface Timing in Long Frame, 10–Bit Frames 5 ...

Page 92

... Freescale Semiconductor, Inc. DCL FSC out B1 TSEN 5.4.4 Master and Slave Mode Operation The MC145572 can be configured for IDL2 master or IDL2 slave operation independently configuration. A logic 1 selects IDL2 master operation and a logic 0 selects IDL2 slave operation. When configured as an IDL2 slave, FSX and FSR can be independently driven by external circuitry. ...

Page 93

... Freescale Semiconductor, Inc. DCL FSR DCHCLK DCH out DCH in Figure 5–24. D Channel Port Timing, IDL2 10–Bit Frames DCL FSR DCHCLK DCH out DCH in Figure 5–25. D Channel Port Timing, IDL2 8–Bit Frames DCL FSC DCHCLK DCH in DCH out Figure 5–26. D Channel Port Timing, IDL2 GCI 2B+D Frames ...

Page 94

... Freescale Semiconductor, Inc. 5.4.6 Timeslot Assigner The MC145572 has a timeslot assigner that can be used when configured for MCU mode. The timeslot assigner is enabled when one or more of OR6(b7, b6, or b5) are set The starting timeslot(s) are programmed into Overlay registers OR0 – OR5. The B1, B2, and D channels are each indepen- dently programmable for both transmit and receive directions ...

Page 95

... Freescale Semiconductor, Inc. Figure 5–27. Timeslot Assigner Data Format Example For More Information On This Product, MOTOROLA Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í ...

Page 96

... Freescale Semiconductor, Inc. Figure 5–28. Timeslot Assigner Data Format Example, B2 Channel Not Enabled For More Information On This Product, 5–24 Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í ...

Page 97

... Freescale Semiconductor, Inc. Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í Í È È È È Í Í Í Í Í Í È È Í Í Í Í Í Í ...

Page 98

... Freescale Semiconductor, Inc. 5.4.7 Timeslot Selection The MC145572, operating at a DCL clock of 4.096 MHz, allows up to 256 start times for data channels (see Table 5–6). Timeslot 0 starts immediately following the FSX/FSR pulse. Timeslot 1 is two DCL pulses later, counted from the rising edge. ...

Page 99

... Freescale Semiconductor, Inc. 5.4.8 IDL2 2B+D Data Alignment to U-Interface Superframe The MC145572 provides signals that indicate the relationship between data transferred over the IDL2 interface and where that data is positioned in the U–interface superframe. In IDL2 short frame and long frame operation, the SFAX and SFAR pins are used to indicate the IDL2 2B+D data frame that corresponds to the first 2B+D block in basic frame 1 of the U– ...

Page 100

... Freescale Semiconductor, Inc. DCL FSR SFAR (OUTPUT) DCL FSR SFAR (OUTPUT) NOTE: The #1 (circled) indicates which 2B+D transfer is the first of the superframe. The clock, DCL, is continuous. DCL FSX SFAX (INPUT) DCL FSX SFAX (INPUT) NOTE: The #1 (circled) indicates which 2B+D transfer is the first of the superframe. The clock, DCL, is continuous. ...

Page 101

... Freescale Semiconductor, Inc. Figure 5–33. IDL2 GCI 2B+D Format For More Information On This Product, MOTOROLA Superframe Alignment Signal MC145572 Go to: www.freescale.com 5–29 ...

Page 102

... Freescale Semiconductor, Inc mode, IDL2 slave operation, any superframe alignment information that may be present on FSC is ignored. ANSI T1.601 defines a 60 mitted Superframe Sync word in the NT–configured MC145572 is delayed 60 bauds or 750 s from the received Superframe Sync word 18,000–foot loop, the total propagation delay in both direc- tions is approximately 6 bauds ...

Page 103

... Freescale Semiconductor, Inc. 5.6.1 U-Interface Loopback A U–interface loopback configuration is shown in Figure 5–34. As the shaded portion of the block diagram shows, this loopback mode exercises virtually the entire U–interface transceiver. The 2B1Q symbols are received from the far–end transmitter, recovered, passed through the IDL2 interface block, and transmitted back to the far– ...

Page 104

... Freescale Semiconductor, Inc. 5.6.2 IDL2 Interface Loopback An IDL2 interface loopback is shown in Figure 5–35. As the shaded portion of the block diagram shows, this loopback mode takes B and D channel data in at the IDL Rx pin and sends the same data back out the IDL2 Tx pin. ...

Page 105

... Freescale Semiconductor, Inc. 5.6.3 Superframe Framer-to-Deframer Loopback A Superframe Framer–to–Deframer loopback is shown in Figure 5–36. As the shaded portion of the block diagram shows, this loopback mode takes B and D channel data in at the D in pin and M channel data via the SCP, performs all of the superframe framing and subsequent deframing functions, and sends the same data back out the D out pin and SCP ...

Page 106

... Freescale Semiconductor, Inc. The procedure to enable the Superframe Framer–to–Deframer loopback for a single LT–configured U–interface transceiver follows, with all numbers given in hexadecimal. NR0 = 8 Assert reset, not required. NR0 = 0 Deassert reset, not required. BR14 = 10 Enable Framer–to–Deframer Loopback, Enable CLKs. Enable CLKs is optional and enables SYSCLK to display an Eye Pattern ...

Page 107

... Freescale Semiconductor, Inc. Below is the procedure to perform the MC145572 Superframe Framer–to–Deframer loopback on the MC145572. Make sure that there pulldown resistor on the SFAX pin. Set BR8(b0 put the selected MC145572 into LT mode. (For devices with the NT/LT pin connected Set BR8(b0 ensure the selected MC145572 mode. (For devices with the NT/LT pin connected Wait 5 seconds for the MC145572 on– ...

Page 108

... Freescale Semiconductor, Inc. Tx SUPERFRAME FIFO FRAMER IDL2 OR GCI INTERFACE D in IDL2 AND GCI CONTROLLER D out FIFO AUTOMATIC ACTIVATION CONTROLLER CONTROL CONTROL PORT INTERFACE INTERFACE & D CHANNEL REGISTER AUTOMATIC eoc PROCESSOR Figure 5–37. External Analog Loop Once the MC145572 has activated, NR1 reads as $B. ...

Page 109

... Freescale Semiconductor, Inc. Procedure to turn off analog loopback when the NT/LT pin is connected (LT mode). BR10 = $01 Enable Overlay Register set. OR8 = $00 Turn off SFAX pin (only required for applications that do not have the 10 k OR9 = $00 Turn off Analog Loopback bit. BR10 = $00 Disable Overlay Register set. ...

Page 110

... Freescale Semiconductor, Inc. For More Information On This Product, 5–38 MC145572 Go to: www.freescale.com MOTOROLA ...

Page 111

... Freescale Semiconductor, Inc. MCU MODE ACTIVATION AND DEACTIVATION 6.1 INTRODUCTION This chapter describes the activation and deactivation procedure for the MC145572 assumed that MC145572 is configured for the IDL2 mode of operation. The material covered in this chapter is useful for all applications strongly recommended that this chapter be read when the GCI mode operation used ...

Page 112

... Freescale Semiconductor, Inc FRAMES TN NT --> NETWORK (LT) NETWORK (LT) --> FRAMES Time Description of Event or State T0 RESET state. T1 Network and NT are awake discontinues transmission, indicating that NT is ready to receive signal. T3 Network responds to termination of signal and begins transmitting signal toward NT. T4 Network begins transmitting SL2 toward NT, indicating that the network is ready to receive SN2. ...

Page 113

... Freescale Semiconductor, Inc. 6.3 ACTIVATION SIGNALS FOR LT MODE When configured as an LT, the MC145572 U–interface transceiver can transmit any of the signals shown in Table 6–2. The actual procedure undertaken by the device using these five signals is de- scribed later in this chapter. Section 4.4.9 describes how to control the transmit framer when it is desired to generate signals for test purposes ...

Page 114

... Freescale Semiconductor, Inc. After the MC145572 ends transmission of SN1 it waits up to 480 ms for LT to transmit a signal, SL1 or SL2. The MC145572 then recovers timing information and transmits SN2. When full duplex operation has been achieved, bits NR1(b3, b1, b0) are each set and SN3 is enabled for transmission. SN3 ...

Page 115

... Freescale Semiconductor, Inc. limit on how long NR1 may read as $A when data transparency is lost. There is a 480–ms time limit on NR1 reading as $8. ANSI T1.601 only indicates that U–interface transceivers must deactivate when Superframe Synchronization or receive signal is lost for more than 480 ms. If the error condition goes away, NR1 returns to $B and an interrupt is generated, if enabled ...

Page 116

... Freescale Semiconductor, Inc. 6.11.2 Indication of Transmit States and Repeater Applications BR8(b7:b4), Frame State 3 through Frame State 0, indicates the current state of the Superframe Framer U–interface repeater, it may be necessary to have NT continue transmitting SN2 until LT–configured MC145572 receives SN3. Software must monitor the transmit state at least once every millisecond to determine when NT starts transmitting SN2 ...

Page 117

... Freescale Semiconductor, Inc. MCU MODE MAINTENANCE CHANNEL OPERATION 7.1 INTRODUCTION When configured for MCU mode operation, the MC145572 provides a very flexible interface to the 4 kbps maintenance channel (M channel), defined in ANSI T1.601–1992. The maintenance channel consists of 48 bits sent by both the LT and NT configured U–interface transceivers during the course of a superframe ...

Page 118

... Freescale Semiconductor, Inc. 7.2 EMBEDDED OPERATIONS SUBCHANNEL The eoc subchannel can operate in one of three modes. The eoc register, R6, can be updated and an interrupt generated on every received eoc frame, and on a successful trinal–check of a new eoc frame. This applies to the NT and LT modes of operation mode, the MC145572 also provides an Automatic eoc Processor for automatic decoding and response to the ANSI T1.601– ...

Page 119

... Freescale Semiconductor, Inc. ANSI T1.601–1992 indicates that data transparency may occur during the last superframe having its act bit equal during the first superframe having its act bit equal the NT mode of operation, the M4 dea bit is checked for a 0 and the logical OR of Verified dea, BR3(b1), and deactivation Request, NR2(b2), ensures that the NT U– ...

Page 120

... Freescale Semiconductor, Inc. The current febe count is maintained in BR4. The count in BR4 is incremented only when the re- ceived febe bit is detected active (0) at the end of the superframe. When OR7(b1 the febe counter does not wrap around when the count reaches $FF. When OR7(b1 the febe counter wraps around and continues counting from 0 ...

Page 121

... Freescale Semiconductor, Inc. - TRANSMITTED M4 UPDATED FROM BR0 - TRANSMITTED M5 AND M6 CHANNELS UPDATED FROM BR2 - TRANSMITTED eoc UPDATED FROM R6 - TxSFS PULSE OUTPUT ON PIN 25 (SEE NOTE DATA 60 2 QUATS DATA QUAT 120 - IRQ1, IRQ2 - BR1 UPDATED FROM RECEIVED M4 CHANNEL - R6 UPDATED FROM RECEIVED eoc CHANNEL NOTE: Due to internal delays, the actual sync word marker on the TxP and TxN pins occurs 8 quats later than the TxSFS pulse. See Figure 10– ...

Page 122

... Freescale Semiconductor, Inc. QUAT 120 - IRQ1, IRQ2 - BR1 UPDATED FROM RECEIVED M4 CHANNEL - R6 UPDATED FROM RECEIVED eoc CHANNEL DATA 60 QUATS DATA QUAT 117 - TRANSMITTED M4 UPDATED FROM BR0 - TRANSMITTED M5 AND M6 CHANNELS UPDATED FROM BR2 - TRANSMITTED eoc UPDATED FROM R6 - TxSFS PULSE OUTPUT ON PIN 25 (SEE NOTE) NOTE: Due to internal delays, the actual sync word marker on the TxP and TxN pins occurs 8 quats later than the TxSFS pulse. See Figure 10– ...

Page 123

... Freescale Semiconductor, Inc. The crc Corrupt mode bit, OR9(b2), modifies the operation of crc Corrupt, BR8(b3). When OR9(b2 the operation of the crc Corrupt bit, BR8(b3), is modified so that a corrupt crc is transmitted only to the end of the current U–interface superframe. Then BR8(b3) is cleared desired to corrupt the transmitted crc again, then BR8(3) must be set again. This is very useful for digital loop carrier applications, since software does not have to clear BR8(b3) in order to guarantee a one– ...

Page 124

... Freescale Semiconductor, Inc. derived from the interrupts generated when the receive maintenance subchannel registers are updated. Figures 7–2 and 7–3 show the appropriate timings possible to configure the TxSFS/ SFAX/S0 pin as SFAX and use the pulse to generate a 12–ms periodic interrupt. Note though that SFAX indicates the 2B+D frame in the IDL2 interface that will be transmitted onto the first 2B+D position in basic frame 1 of the U– ...

Page 125

... Freescale Semiconductor, Inc. GCI MODE FUNCTIONAL DESCRIPTION 8.1 FUNCTIONAL OVERVIEW The MC145572 is configurable for the General Circuit Interface or GCI operation. GCI is a time divi- sion multiplex bus, that combines the ISDN 2B+D data and control/status information onto four signal pins. There are two clocks per data bit and a single frame synchronization pulse, FSC. ...

Page 126

... Freescale Semiconductor, Inc. Figure 8–1. MC145572 Configuration for GCI Operation For More Information On This Product, 8–2 MC145572FN MC145572 Go to: www.freescale.com MOTOROLA ...

Page 127

... Freescale Semiconductor, Inc. 8.2 INTERFACE SIGNALS Seven signal pins are available for the time division multiplex bus interface in GCI mode. S2, S1, S0 — Used to select the active GCI channel in multiplexed GCI frames. DCL — 2x data clock. FSC — The 8 kHz frame synchronization pulse. ...

Page 128

... Freescale Semiconductor, Inc. Figure 8–2. Single Channel GCI Format For More Information On This Product, 8–4 Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î MC145572 Go to: www.freescale.com MOTOROLA ...

Page 129

... Freescale Semiconductor, Inc. Figure 8–3. Multiplexed GCI Format Example For More Information On This Product, MOTOROLA MC145572 Go to: www.freescale.com 8–5 ...

Page 130

... Freescale Semiconductor, Inc. 8.3.1 Monitor Channel Operation The Monitor channel is used to access the internal registers of the MC145572 in order to support U–interface maintenance channel operations. All Monitor channel messages are two bytes in length. Each byte is sent twice to permit the receiving GCI device to verify data integrity. In ISDN applications, the Monitor channel is used for access to the U– ...

Page 131

... Freescale Semiconductor, Inc. FSC 125 s NULL E BYTE 1 E BYTE out Figure 8–4. Monitor Channel Access Protocol FSC 125 s NULL E BYTE 1 E BYTE out Figure 8–5. Monitor Channel Protocol with Delay BYTE 1 BYTE 1 BYTE 2 BYTE out FSC WRITE COMMAND 1 Figure 8–6. Monitor Channel Register Write Sequence ...

Page 132

... Freescale Semiconductor, Inc. BYTE 1 BYTE out FSC READ COMMAND 1 Figure 8–7. Monitor Channel Register Read Sequence BYTE 1 BYTE 1 BYTE 2 BYTE out FSC INTERRUPT INDICATION 1 Figure 8–8. Monitor Channel Multiple Interrupt Indications Sequence For More Information On This Product, 8– BYTE 1 BYTE 1 BYTE 2 BYTE 2 ...

Page 133

... Freescale Semiconductor, Inc. Table 8–3. Monitor Channel Commands Byte 1 msb b17 b16 b15 b14 b13 b12 ba3 ba2 ba3 ba2 na3 na2 na3 na2 NOTES: 1. For byte register accesses, the address range of ba3, ba2, ba1, ba0 is hexadecimal 0 – F. The bits d7 through d0 are data that is written to the byte register. 2. For nibble register accesses, the address range of na3, na2, na1, na0 is hexadecimal 0 – ...

Page 134

... Freescale Semiconductor, Inc. 8.3.2.2 MONITOR CHANNEL RESPONSE MESSAGES The Monitor channel response messages are transmitted onto the GCI Monitor channel by the MC145572 in response to a register read command. The Monitor channel response messages are given in Table 8–4. Table 8–4. Monitor Channel Response Messages ...

Page 135

... Freescale Semiconductor, Inc. 8.3.3 Command/Indicate Channel Operation The Command/Indicate, or C/I channel, is used to activate and deactivate the MC145572. Some control functions such as loopbacks are also supported over the C/I channel. C/I codes are four bits in length and must be received for two consecutive GCI frames before they are acted upon. ...

Page 136

... Freescale Semiconductor, Inc. 8.4 GCI ACTIVATION AND DEACTIVATION TIME DIAGRAMS This section contains the time flow diagrams that detail the various activation and deactivation scenar- ios for the MC145572 U–interface transceiver. Figures 8–9 through 8–17 are the activation diagrams for the MC145572 operating in GCI mode. Figures 8–18 and 8–19 are the activation state diagrams for NT and LT mode operation ...

Page 137

... Freescale Semiconductor, Inc. S/T Î Î Î Î Î Î Î INFO 0 DC Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î INFO 0 DI Î Î Î Î Î Î Î ...

Page 138

... Freescale Semiconductor, Inc. S/T Î Î Î Î Î Î Î Î Î AI Î Î Î Î Î Î Î Î Î aip_tp, act, dea, Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 139

... Freescale Semiconductor, Inc. S/T Î Î Î Î Î Î Î Î Î X INFO 0 DC Î Î Î Î Î Î Î Î Î linkup, SFS, aip_tp Î Î Î Î Î Î Î Î Î INFO 0 Î Î DI Î Î Î Î Î Î Î ...

Page 140

... Freescale Semiconductor, Inc. S/T Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î INFO 4 AI Î Î Î Î Î Î Î Î INFO 3 Î Î Î Î Î Î Î Î AI Î Î ...

Page 141

... Freescale Semiconductor, Inc. S/T Î Î Î Î Î Î Î Î INFO 0 Î Î Î Î Î Î Î Î DC Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î INFO 0 DI Î Î ...

Page 142

... Freescale Semiconductor, Inc. S/T Î Î Î Î Î Î Î Î INFO 4 linkup, SFS, aip_tp, AI Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î INFO 3 AI Î Î Î Î Î Î Î Î ...

Page 143

... Freescale Semiconductor, Inc. 8.5 GCI MASTER AND SLAVE MODE OPERATION The MC145572 can be configured for GCI master or GCI slave operation independently configuration. When the pin M/S is pulled low to V SS, GCI slave operation is selected. When the pin M/S is pulled high GCI master operation is selected. When configured as a slave, FSC is an input driven by external circuitry ...

Page 144

... Freescale Semiconductor, Inc. Figure 8–18. NT Mode GCI State Diagram (Sheet For More Information On This Product, 8–20 MC145572 Go to: www.freescale.com MOTOROLA ...

Page 145

... Freescale Semiconductor, Inc. A SFS=1 B Wait_AI RSY START 480 ms TIMER C IND = RSY SFS=1, aip_tp=1 NR1 = 1000 Tx = SN3 D 480 ms TIMEOUT rx_dea SET EI F Wait_AI rx_dea=0 SAVE COEFFICIENTS ENABLE WARM START IND = AR NR1 = 1011 SN3 rx_SL0 NORMAL TO TEAR DOWN rx_dea=0 SAVE COEFFICIENTS ENABLE WARM START ...

Page 146

... Freescale Semiconductor, Inc. Figure 8–19. LT Mode GCI State Diagram (Sheet For More Information On This Product, 8–22 MC145572 Go to: www.freescale.com MOTOROLA ...

Page 147

... Freescale Semiconductor, Inc NOTES “x” in the NR1 bit means that the bit remains unchanged from its value in a previous state The transmitted M4 channel bits remain unchanged between states unless a change is 3. SL3T is SL3 with transparent data transmission. 4. The state “Normal Operation” is the state in which the MC145572 operates when it is fully 5. Linkup = NR1(b3), SFS = NR1(b1), aip_tp = NR1(b0). Figure 8– ...

Page 148

... Freescale Semiconductor, Inc. For More Information On This Product, 8–24 MC145572 Go to: www.freescale.com MOTOROLA ...

Page 149

... Freescale Semiconductor, Inc. MCU MODE PROGRAMMING SUGGESTIONS 9.1 INTRODUCTION This chapter is a guide for writing software for the MC145572. It provides several pseudo–code exam- ples on how to initialize and activate the MC145572 U–interface transceiver. NT and LT initiated activation procedures are given, using both the automatic and non–automatic eoc modes. This chapter also contains sample initialization routines for IDL– ...

Page 150

... Freescale Semiconductor, Inc. channel interrupt service routine, NTISR1, is also provided in Section 9.2.1. Procedure NTINIT2 in Section 9.2.2 initializes the MC145572 for non–automatic eoc operation when in the NT mode. The corresponding sample high level embedded operations channel interrupt service routine, NTISR2, is also provided in Section 9.2.2. Procedure LTINIT1 in Section 9.3 initializes the MC145572 when it is operated in LT mode ...

Page 151

... Freescale Semiconductor, Inc. Procedure NTINIT1() /* PURPOSE: The initialization procedure NTINIT1 puts the NT configured U–interface transceiver into automatic eoc mode and selects the M4 channel trinal consecutive check mode of operation. It also sets default values for the M4, M5, and M6 channels. Activation interrupts are also enabled ...

Page 152

... Freescale Semiconductor, Inc. 9.2.2 NT Non-Automatic eoc Mode Initialization and Activation The MC145572 can be operated with eoc frame trinal checking and eoc interrupts enabled so an external microcontroller may handle all eoc commands in software. Note that the MC145572 still per- forms eoc frame trinal checking, thus relieving the external microcontroller of this task. The M4 channel dual consecutive check mode is enabled. The examples in this section configure an NT U– ...

Page 153

... Freescale Semiconductor, Inc. Procedure NTISR2() /* PURPOSE: The interrupt service routine NTISR2 checks for Linkup with Super frame Sync or for an Error Indication. If linkup is achieved, the febe and nebe counters are cleared and the M4 act bit is set check of the S/T–interface indicates that it is active. If the Error Indication status bit, NR1(b2), is set to 1, appropriate measures can be taken ...

Page 154

... Freescale Semiconductor, Inc. 9.2.3 LT Mode Initialization and Activation LT initialization is very similar to NT initialization except that the automatic eoc mode is not available. Trinal checking of received eoc commands is enabled. When the U–interface transceiver is operated as an LT, the software initiates eoc messages by writing into R6. Correct operation of the eoc mes- sage at the NT1, as defined in ANSI T1.601– ...

Page 155

... Freescale Semiconductor, Inc. Procedure LTISR1() /* PURPOSE: The interrupt service routine LTISR1 checks for Linkup with Super frame Sync or for an Error Indication. If linkup is achieved, the febe and nebe counters are cleared and the M4 act bit is set check is made for correct reception of the eoc message by the NT1. ...

Page 156

... Freescale Semiconductor, Inc. 9.3 TIMESLOT ASSIGNER PROGRAMMING EXAMPLE In modern Central Office Switches (COS) or Private Branch Exchanges (PBXs), a Time Division Multi- plex (TDM) bus may carry data from several different U–interfaces. The MC145572 is designed with a flexible Timeslot Assigner (TSAC), allowing it to transmit and receive 2B+D data in any timeslot on a TDM bus. With the MC145572s TSAC, B, and D channel timeslots can be assigned an any 2– ...

Page 157

... Freescale Semiconductor, Inc. Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 158

... Freescale Semiconductor, Inc. Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 159

... Freescale Semiconductor, Inc. 9.4 GCI 2B+D MODE PROGRAMMING EXAMPLE This example shows how to program the MC145572 when the GCI 2B+D format is selected instead of IDL 8– and 10–bit modes. See Section 5.4.3 for a description of the GCI 2B+D mode. Procedure GCI2B+Dinit(); /* PURPOSE: Program GCI timeslot in IDL–2 GCI 2B+D data format INITIAL CONDITIONS: MC145572 configured for IDL– ...

Page 160

... Freescale Semiconductor, Inc. Procedure BLER_init /* PURPOSE: BLER_init initializes the febe/nebe counters, enables febe/nebe rollover, and en- ables the 1.2 second interrupt. Initialization of the febe/nebe registers should be done upon activation as shown in the NT and TE activation examples previously mentioned in this section. */ BEGIN BR4 <– 00; ...

Page 161

... Freescale Semiconductor, Inc. 9.6 D CHANNEL COMMUNICATION VIA THE SERIAL OR PARALLEL CONTROL PORT In non–ISDN applications, such as pair–gain multiplexing often necessary to communicate low– speed status information. The MC145572 provides a simple means to transmit this type of status information over the D channel of the U–interface. ...

Page 162

... Freescale Semiconductor, Inc. procedure DCH_init /* PURPOSE: DCH_init initializes the D channel SCP/PCP communications and also activates the MC145572. BEGIN NR0(b3) <– Assert software reset. Only required NR0(b3) <– De–assert software reset. Only required at power–up initialization.*/ BR10(b1) <– Enable SCP/PCP D channel read/write access through OR12 */ NR4 < ...

Page 163

... Freescale Semiconductor, Inc. 10.1 ABSOLUTE MAXIMUM RATINGS (Voltages Referenced Rating DC Supply Voltage Voltage, Any Pin Current, Any Pin (see Note) Operating Temperature Storage Temperature NOTE: Except for TxP, and TxN. 10.2 RECOMMENDED OPERATING CONDITIONS (Voltages Referenced – Parameter DC Supply Voltage Current Sourced from CAP3V pin @ 2 ...

Page 164

... Freescale Semiconductor, Inc. 10.5 DC ELECTRICAL CHARACTERISTICS ( 5 5 – Parameter High–Level Input Voltage, Except FREQREF and RESET Low–Level Input Voltage, Except FREQREF and RESET High–Level Input Voltage, FREQREF and RESET Low–Level Input Voltage, FREQREF and RESET High–Level Output Voltage ( – 400 A) Low– ...

Page 165

... Freescale Semiconductor, Inc. 10.7 IDL2 TIMING 10.7.1 IDL2 Master Short Frame Sync Timing, 8- and TSAC Formats Ref. No. 1 FSR or FSX Period 2 Delay From the Rising Edge of DCL to the Rising Edge of FSX or FSR 3 Delay From the Rising Edge of DCL to the Falling Edge of ...

Page 166

... Freescale Semiconductor, Inc. FSX OR FSR 3 2 DCL 7 D out TSEN Figure 10–1. IDL Short Frame Sync Master Timing, 8– and 10–Bit Formats and TSAC Formats For More Information On This Product, 10– MC145572 Go to: www.freescale.com 9 13 MOTOROLA ...

Page 167

... Freescale Semiconductor, Inc. 10.7.2 IDL2 Slave Short Frame Sync Timing, 8- and 10-Bit Formats Ref. No. 14 FSR or FSX Period 15 FSR or FSX High Before the Falling Edge of DCL (FSR or FSX Setup Time) 16 FSR or FSX High After the Falling Edge of DCL (FSR or FSX Hold Time) 17 Delay From Rising Edge of DCL to Low– ...

Page 168

... Freescale Semiconductor, Inc. Figure 10–2. IDL Short Frame Sync Slave Timing, 8– and 10–Bit Formats For More Information On This Product, 10–6 MC145572 Go to: www.freescale.com MOTOROLA ...

Page 169

... Freescale Semiconductor, Inc. 10.7.3 IDL2 Master Long Frame Sync, 8- and 10-Bit Formats Ref. No. 27 FSR or FSX Period 28 Delay From Rising Edge of DCL to Rising Edge of FSR or FSX 29 Delay From Rising Edge of DCL to Falling Edge of FSR or FSX 30 Delay From Rising Edge of FSR to Low–Z and Valid Data on ...

Page 170

... Freescale Semiconductor, Inc. 10.7.4 IDL2 Slave Long Frame Sync, 8- and 10-Bit Formats Ref. No. 40 FSR or FSX Period 41 FSR or FSX High Before the Falling Edge of DCL (FSR or FSX Setup Time) 42 FSR or FSX High After the Falling Edge of DCL (FSR or FSX Hold Time) ...

Page 171

... Freescale Semiconductor, Inc. Figure 10–4. Long Frame Sync Slave Timing, 8– and 10–Bit Formats For More Information On This Product, MOTOROLA MC145572 Go to: www.freescale.com 10–9 ...

Page 172

... Freescale Semiconductor, Inc. 10.8 GCI TIMING Ref. No. 53 Delay From Rising Edge of DCL to FSC Output High 54 Delay From Rising Edge of DCL to FSC Output Low (Normal Frame) 55 Delay From Rising Edge of DCL to FSC Output Low (Superframe Marker) 56 FSC Input High Before the Falling Edge of DCL (FSC Setup Time) 57 FSC Input High After the Falling Edge of DCL (FSC Hold Time — ...

Page 173

... Freescale Semiconductor, Inc. For More Information On This Product, MOTOROLA Figure 10–5. GCI Timing MC145572 Go to: www.freescale.com 10–11 ...

Page 174

... Freescale Semiconductor, Inc. 10.9 D-CHANNEL PORT TIMING 10.9.1 IDL2 (Master or Slave) Short Frame Sync 8-Bit Format, D Channel Port Timing Ref. No. 71 Delay From DCL Rising Edge to DCHCLK Rising Edge 72 Delay From DCHCLK Rising Edge to Data Valid on DCH out 73 Data Valid on DCH in Before Falling Edge of DCHCLK (DCH in ...

Page 175

... Freescale Semiconductor, Inc. Figure 10–6. IDL2 (Master or Slave) Short Frame Sync 8–Bit Format, For More Information On This Product, MOTOROLA D Channel Port Timing MC145572 Go to: www.freescale.com 10–13 ...

Page 176

... Freescale Semiconductor, Inc. 10.9.2 IDL2 (Master or Slave) Short Frame Sync 10-Bit Format, D Channel Port Timing Ref. No. 75 Delay From DCL Rising Edge to DCHCLK Rising Edge 76 Delay From DCHCLK Rising Edge to Data Valid on DCH out 77 Data Valid on DCH in Before Falling Edge of DCHCLK (DCH in ...

Page 177

... Freescale Semiconductor, Inc. Figure 10–7. IDL2 (Master or Slave) Short Frame Sync 10–Bit Format, For More Information On This Product, MOTOROLA D Channel Port Timing MC145572 Go to: www.freescale.com 10–15 ...

Page 178

... Freescale Semiconductor, Inc. 10.9.3 IDL2 (Master or Slave) Long Frame Sync 8-Bit Format, D Channel Port Timing Ref. No. 79 Delay From DCL Rising Edge to DCHCLK Rising Edge 80 Delay From DCHCLK Rising Edge to Data Valid on DCH out 81 Data Valid on DCH in Before Falling Edge of DCHCLK (DCH in ...

Page 179

... Freescale Semiconductor, Inc. Figure 10–8. IDL2 (Master or Slave) Long Frame Sync 8–Bit Format, For More Information On This Product, MOTOROLA D Channel Port Timing MC145572 Go to: www.freescale.com 10–17 ...

Page 180

... Freescale Semiconductor, Inc. 10.9.4 IDL2 (Master or Slave) Long Frame Sync 10-Bit Format, D Channel Port Timing Ref. No. 83 Delay From DCL Rising Edge to DCHCLK Rising Edge 84 Delay From DCHCLK Rising Edge to Data Valid on DCH out 85 Data Valid on DCH in Before Falling Edge of DCHCLK (DCH in ...

Page 181

... Freescale Semiconductor, Inc. Figure 10–9. IDL2 (Master or Slave) Long Frame Sync 10–Bit Format, For More Information On This Product, MOTOROLA D Channel Port Timing MC145572 Go to: www.freescale.com 10–19 ...

Page 182

... Freescale Semiconductor, Inc. 10.10 SUPERFRAME TRANSMIT AND RECEIVE (SFAX/SFAR) TIMING 10.10.1 SFAX Input Timing in IDL2 (Master or Slave) Short Frame Mode Ref. No. 91 FSX Period 92 SFAX Period 93 SFAX Input High Before Falling Edge of DCL (SFAX Setup Time) 94 SFAX Input High After Falling Edge of DCL (SFAX Hold Time) NOTES: 1 ...

Page 183

... Freescale Semiconductor, Inc. 10.10.2 SFAX Input Timing in IDL2 (Master or Slave) Long Frame Mode Ref. No. 95 Delay From Rising Edge of DCL to Rising Edge of FSR or FSX 96 FSR or FSX High Before the Falling Edge of DCL (FSR or FSX Setup Time) 97 FSR or FSX High After the Falling Edge of DCL (FSR or FSX ...

Page 184

... Freescale Semiconductor, Inc. Figure 10–11. SFAX Input Timing in IDL2 (Master or Slave) For More Information On This Product, 10–22 Long Frame Mode MC145572 Go to: www.freescale.com MOTOROLA ...

Page 185

... Freescale Semiconductor, Inc. 10.10.3 SFAX/SFAR Output Timing in IDL2 (Master or Slave) Short Frame Mode Ref. No. 102 FSX Period 103 SFAX Period 104 Delay From the Rising Edge of DCL to the Rising Edge of FSAR or FSAX 105 Delay From the Rising Edge of DCL to the Rising Edge of ...

Page 186

... Freescale Semiconductor, Inc. Figure 10–12. SFAX/SFAR Output Timing in IDL2 Short Frame Mode For More Information On This Product, 10–24 (Master or Slave) MC145572 Go to: www.freescale.com MOTOROLA ...

Page 187

... Freescale Semiconductor, Inc. 10.10.4 SFAX/SFAR Output Timing in IDL2 (Master or Slave) Long Frame Mode Ref. No. 106 FSX or FSR Period 107 SFAX or SFAR Period 108 Delay From the Rising Edge of FSR or FSX to the Rising Edge of SFAR or SFAX NOTES: 1. See Section 10.7 for FSX jitter requirements and specifications. ...

Page 188

... Freescale Semiconductor, Inc. Figure 10–13. SFAX/SFAR Output Timing in IDL2 Long Frame Mode For More Information On This Product, 10–26 (Master or Slave) MC145572 Go to: www.freescale.com MOTOROLA ...

Page 189

... Freescale Semiconductor, Inc. 10.11 PARALLEL CONTROL PORT TIMING 10.11.1 Parallel Control Port Write Timing Ref. No. 109 CS Low 110 CS High 111 R/W Low Before CS Rising Edge (R/W Setup Time) 112 R/W Low After CS Rising Edge (R/W Hold Time) 113 D0 – D7 Valid Before the Rising Edge of CS (Data Setup Time) 114 D0 – ...

Page 190

... Freescale Semiconductor, Inc. 10.11.2 Parallel Control Port Read Timing Ref. No. 115 CS Low 116 CS High 117 R/W High Before CS Falling Edge (R/W Setup Time) 118 R/W High After CS Rising Edge (R/W Hold Time) 119 D0 – D7 Valid After the Falling Edge of CS (Read Access Time) 120 D0 – ...

Page 191

... Freescale Semiconductor, Inc. 10.12 SWITCHING CHARACTERISTICS FOR SCP INTERFACE ( 5 – pF; See Figure 10–2) Ref. No. 121 SCPCLK Rising Edge Before SCPEN(L) Falling Edge 122 SCPEN Falling Edge Before SCPCLK Rising Edge 123 SCPRx Data Valid Before SCPCLK Rising Edge (Setup Time) ...

Page 192

... Freescale Semiconductor, Inc. Figure 10–16. SCP Interface Timing For More Information On This Product, 10–30 MC145572 Go to: www.freescale.com MOTOROLA ...

Page 193

... Freescale Semiconductor, Inc. 10.13 SWITCHING CHARACTERISTICS FOR SYSCLK AND EYEDATA ( 5 – pF; See Figure 10–13) Ref. No. 134 SYSCLK Rising Edge to EYEDATA Valid NOTE: Measurements are made from the point at which they achieve their guaranteed minimum or maximum logic levels. Figure 10–17. SYSCLK and EYEDATA Timing ...

Page 194

... Freescale Semiconductor, Inc. 10.14 SWITCHING CHARACTERISTICS FOR CRYSTAL INPUT, CLKOUT, BUFXTAL, AND FREQREF ( 5 – pF; See Figure 10–14) Ref. No. 135a FREQREF Minimum Pulse Width Low (LT Mode Only) 135b FREQREF Minimum Pulse Width High (LT Mode Only) 136 BUFXTAL Duty Cycle at 20.48 MHz ...

Page 195

... Freescale Semiconductor, Inc. 10.15 SWITCHING CHARACTERISTICS FOR BAUD CLOCKS ( 5 – pF; See Figure 10–15) Ref. No. 147 2B1Q Baud Period 148 Start of 2B1Q Baud to Tx Baud Clock Rising Edge 149 Tx Baud Clock Width High, Rx Baud Clock TxSFS 150 Superframe Period NOTE: Measurements are made from the point at which they achieve their guaranteed minimum or maximum logic levels. ...

Page 196

... Freescale Semiconductor, Inc. For More Information On This Product, 10–34 MC145572 Go to: www.freescale.com MOTOROLA ...

Page 197

... Freescale Semiconductor, Inc. 11.1 PIN ASSIGNMENTS PIN 1 INDICATOR ref ref TxP TxN 12 PAR/SER 13 RESET 14 NT/LT 15 M/S 16 IRQ 17 For More Information On This Product, MOTOROLA MECHANICAL DATA MC145572FN 35 44 LEAD PLCC 34 (TOP VIEW Figure 11–1. MC145572FN Pin Assignment MC145572 Go to: www.freescale.com 11 EYEDATA/D5/S2/DCHCLK/TxOFF BUFXTAL/D4 ...

Page 198

... Freescale Semiconductor, Inc ref ref TxP TxN 39 PAR/SER 40 RESET 41 NT/LT 42 M/S 43 IRQ 44 PIN 1 INDICATOR Figure 11–2. MC145572PB Pin Assignment For More Information On This Product, 11–2 22 EYEDATA/D5/S2/DCHCLK/TxOFF 21 BUFXTAL/ 15.36 CLKOUT/D3 MC145572PB 44 LEAD TQFP 17 4.096 CLKOUT/D2 (TOP VIEW) 16 XTAL 15 XTAL 14 DCL 13 D out MC145572 Go to: www ...

Page 199

... Freescale Semiconductor, Inc. 11.2 PACKAGE DIMENSIONS -N- Y BRK - 0.010 (0.250 NOTES: 1. DATUMS AND N DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM T , SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS (0.010) 0.25 PER SIDE ...

Page 200

... Freescale Semiconductor, Inc. L –Z– –T– L DETAIL 0.20 (0.008 0.05 (0.002) T-U S 0.20 (0.008 VIEW AD Figure 11–4. MC145572PB Mechanical Outline For More Information On This Product, 11–4 TQFP PACKAGE CASE 824D– –U– T T DETAIL AD –AB– 0.10 (0.004) –AC– MC145572 Go to: www.freescale.com – ...

Related keywords