T7115AMCD LSI, T7115AMCD Datasheet - Page 28

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T7115AMCD

Manufacturer Part Number
T7115AMCD
Description
Manufacturer
LSI
Datasheet

Specifications of T7115AMCD

Package Type
PLCC
Lead Free Status / Rohs Status
Not Compliant
T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
3-State Mode
The HIFI-64 can be placed in a high-impedance mode for test purposes. In this configuration, all output pins are
placed in a 3-state condition. This can be accomplished in two different ways:
1. Asserting the RESET pin 3-states all outputs, clears both the transmit and receive FIFOs, and resets all internal
2. Setting the 3STATE bit (R6—B6) to 1 3-states all outputs without affecting the states of internal registers and
Setting the receiver reset (RRES) and the transmitter reset (TRES) bits in the operation control register
(R6—B4,B5) to 1 simultaneously causes a FIFO and register reset to reset values (outputs are not 3-stated).
Other
The HIFI-64 can be instructed to transmit a bad CRC for test purposes by programming the TBCRC bit in register
14 (R14—B7) to 1. Bad CRCs are transmitted until the TBCRC bit is cleared. The TEST bit in AR11 is used for
manufacture testing and should always be programmed low (0) by the host microprocessor.
Powerdown Mode
The HIFI-64 can be placed in a low-power mode when not in use by setting the PDWN bit in register 6 (R6—B7) to
1. This has the effect of stopping data clock input signals (CLKR and CLKX) from propagating internally and results
in very low power dissipation. Reads and writes to the HIFI-64 can continue normally. The low-power mode is
exited by clearing the PDWN bit (R6—B7) to 0.
Registers
The HIFI-64 contains 19 registers (R0—R15 and AR11—AR13). Registers 11, 12, and 13 have alternate meanings
depending on the value of the ALT bit in the Chip Configuration Register (R0—B4). The alternate registers are
accessed by setting the ALT bit (R0—B4) to 1. All subsequent addressing of registers 11 through 13 then refers to
the alternate registers (AR11—AR13). Returning to the foreground register set is accomplished by clearing the ALT
bit (R0—B4) to 0. The primary function of the alternate registers is for transparent-mode operation.
A summary of the HIFI-64 register set is given in Table 6.
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registers to their default values. A full chip reset occurs with or without a clock input.
FIFOs. This state lasts until both
bit regardless of the register address. Registers can be written while the 3STATE bit is enabled.
(continued)
CS
and
RD
are held low; that is, the first read of the HIFI-64 resets the 3STATE
Lucent Technologies Inc.
Data Sheet
April 1997

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