T7115AMCD LSI, T7115AMCD Datasheet - Page 38

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Table 17. Register R10—Transmitter Time-Slot Offset Control Register
38
R10—B7
Register
DXI
R10
R10
R10
(0)
R10—B6
B(0—5)
TLBIT
Bit
B6
B7
(1)
TTSOF0—TTSOF5 Transmitter Time-Slot Offset. The value of these 6 bits,
R10—B5
TTSOF5
(continued)
(0)
Symbol
TLBIT
DXI
R10—B4
TTSOF4
(0)
coded in binary with bit 0 being the LSB, specifies the number
of time slots to delay between the beginning of the first locat-
able time slot and the beginning of a new virtual TDM frame
(i.e., the time slot defined by the user as time slot 0). See Fig-
ure 5 for an example of using the TTSOF bits.
Transmit Least Significant Bit First. This bit is used to con-
trol whether the least significant or most significant data bit is
transmitted first. The least significant bit of transmit data is
defined as the transmit FIFO data bit written by the host on the
AD0 pin. When TLBIT is 0, the most significant bit of data is
transmitted first, and when TLBIT is set to 1, the least signifi-
cant bit of data is transmitted first.
TLBIT has no meaning when not in the TDM highway mode
(i.e., HWYEN, R0—B7 = 0). Data in non-TDM highway mode is
always least significant bit first.
Transmit Data Inverted. If this bit is set to 1, the serial data
output is inverted before transmission.
R10—B3
TTSOF3
(0)
R10—B2
Name/Function
TTSOF2
(0)
R10—B1
TTSOF1
Lucent Technologies Inc.
(0)
Data Sheet
April 1997
R10—B0
TTSOF0
(0)