T7115AMCD LSI, T7115AMCD Datasheet - Page 44

• Manufacturer Part Number: T7115AMCD
• Manufacturer: LSI

Specifications of T7115AMCD

• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

T7121 HDLC Interface for ISDN (HIFI-64)
Functional Description
Table 25. Register R15—Interrupt Status Register
* In transparent mode (TRANS, AR11—B6 = 1), TDONE defaults to 1 when a transmitter reset (TRES, R6—B5 = 1) is performed.
44
Register
R15—B7
R15
R15
R15
R15
R15
R15
R15
R15
(–)
0
Bit
B0
B1
B2
B3
B4
B5
B6
B7
R15—B6
RIDL
RESERVED Program to 0.
(0)
OVERUN
UNDABT
Symbol
TDONE
RIDL
EOF
RF
TE
OVERUN
R15—B5
(continued)
Transmit Done. This status bit is set to 1 when transmission of the current
HDLC frame has been completed, either after the last bit of the closing flag or
after the last bit of an abort sequence. In the transparent mode (AR11—B6 = 1),
this status bit is set when the transmit FIFO is completely empty. A hardware
interrupt is generated only if the corresponding interrupt-enable bit (R14—B0) is
set. This status bit is cleared to 0 by a read of register 15.
Transmitter Empty. If this bit is set to 1, the HDLC transmit FIFO is at or below
the programmed depth (see register 1). A hardware interrupt is generated only if
the corresponding interrupt-enable bit (R14—B1) is set. If DINT (R0—B0) is 0,
this status bit is cleared by a read of register 15. If DINT (R0—B0) is set to 1,
this bit actually represents the dynamic transmit empty condition, and is cleared
to 0 only when the transmit FIFO is loaded above the programmed empty level.
Underrun Abort. A 1 indicates that an abort was transmitted because of a
transmit FIFO underrun. A hardware interrupt is generated only if the corre-
sponding interrupt-enable bit (R14—B2) is set. This status bit is cleared to 0 by
a read of register 15. This bit must be cleared to 0 before further transmission of
data is allowed. This interrupt is not generated in transparent mode.
Receiver Full. This bit is set to 1 when the receive FIFO is at or above the pro-
grammed full level (see register 5). A hardware interrupt is generated if the cor-
responding interrupt-enable bit (R14—B3) is set. If DINT (R0—B0) is 0, this
status bit is cleared to 0 by a read of register 15. If DINT (R0—B0) is set to 1,
then this bit actually represents the dynamic receive-full condition and is cleared
only when the receive FIFO is read (or emptied) below the programmed full
level.
Receive End-of-Frame. This bit is set to 1 when the receiver has finished
receiving a frame. It becomes 1 upon reception of the last bit of the closing flag
of a frame or the last bit of an abort sequence. A hardware interrupt is generated
only if the corresponding interrupt-enable bit (R14—B4) is set. This status bit is
cleared to 0 by a read of register 15. This bit is not generated in transparent
mode.
Receiver Overrun. This bit is set to 1 when the receive FIFO has overrun its
capacity. A hardware interrupt is generated only if the corresponding interrupt-
enable bit (R14—B5) is set. This status bit is cleared to 0 by a read of register
15.
Receiver Idle. This bit is set to 1 when the HIFI-64 HDLC receiver is idle (i.e.,
15 or more consecutive 1s have been received). A hardware interrupt is gener-
ated only if the corresponding interrupt-enable bit (R14—B6) is set. This status
bit is cleared to 0 by a read of register 15.
(0)
R15—B4
REOF
(0)
R15—B3
RF
(0)
Name/Function
R15—B2
UNDABT
(0)
R15—B1
Lucent Technologies Inc.
TE
(1)
Data Sheet
April 1997
R15—B0
TDONE
(0)*