ADP5042ACPZ-1 Analog Devices Inc, ADP5042ACPZ-1 Datasheet

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ADP5042ACPZ-1

Manufacturer Part Number
ADP5042ACPZ-1
Description
PMU, 2 LDO, DUAL BUCK, 20LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADP5042ACPZ-1

Rohs Compliant
YES
Supply Voltage
5.5V
No. Of Step-down Dc - Dc Converters
1
No. Of Ldo Regulators
2
No. Of Pins
20
No. Of Regulated Outputs
3
Operating Temperature Range
-40°C To +125°C
Base Number
5042
FEATURES
Input voltage range: 2.3 V to 5.5 V
One 0.8 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Initial regulator accuracy: ±1%
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open drain processor reset with threshold monitoring
±1.5% threshold accuracy over the full temperate range
Guaranteed reset output valid to V
Dual watchdog for secure systems
Buck key specifications
LDOs key specifications
GENERAL DESCRIPTION
The ADP5042 combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulator enables
use of tiny multilayer external components and minimizes the
board space.
The MODE pin selects the buck mode of operation. When set
to logic high, the buck regulators operate in forced PWM mode.
When the MODE pin is set to logic low, the buck regulators
operate in PWM mode when the load is around the nominal
value. When the load current falls below a predefined threshold
the regulator operates in power save mode (PSM) improving
the light-load efficiency.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Watchdog 1 controls reset
Watchdog 2 controls reset and regulators power cycle
Current mode topology for excellent transient response
3 MHz operating frequency
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PFM/PSM modes
100% duty cycle low dropout mode
Low V
Stable with1 μF ceramic output capacitors
High PSRR, 60 dB PSRR up to 1 kHz/10 kHz
Low output noise
Low dropout voltage: 150 mV at 300 mA load
−40°C to +125°C junction temperature range
110 μV rms typical output noise at V
IN
from 1.7 V to 5.5 V
CC
= 1 V
OUT
= 2.8 V
Micro PMU with 0.8 A Buck, Two 300 mA LDOs
Supervisory, Watchdog and Manual Reset
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
VIN1 = 2.3V
VIN2 = 1.7V
VIN3 = 1.7V
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP5042 LDOs extend the battery life of
portable devices. The two LDOs maintain power supply
rejection greater than 60 dB for frequencies as high as 10 kHz
while operating with a low headroom voltage.
Each regulator is activated by a high level on the respective
enable pin. The ADP5042 is available with factory programmable
default output voltages and can be set to a wide range of options.
The ADP5042 contains supervisory circuits that monitor
power supply voltage levels and code execution integrity in
microprocessor-based systems. They also provide power-on
reset signals. An on-chip dual watchdog timer can reset the
microprocessor or power cycle the system (Watchdog 2) if it
fails to strobe within a preset timeout period.
TO 5.5V
TO 5.5V
TO 5.5V
4.7µF
1µF
1µF
C1
C3
C5
R
FILT
HIGH LEVEL BLOCK DIAGRAM
= 30Ω
OFF
OFF
OFF
ON
ON
ON
AVIN
VIN3
VIN1
VIN2
EN1
EN2
EN3
MR
©2010 Analog Devices, Inc. All rights reserved.
AVIN
AVIN
EN_BK
EN_LDO1
EN_LDO2
(ANALOG)
(DIGITAL)
Figure 1.
BUCK
LDO1
LDO2
AGND
MODE
VOUT2
nRSTO
VOUT3
WSTAT
SW
VOUT1
PGND
WDI1
WDI2
ADP5042
FPWM
www.analog.com
1µH
L1
PSM/PWM
C2
1µF
C4
1µF
C6
10µF
V
300mA
V
300mA
V
800mA
OUT2
OUT3
OUT1
AT
AT
AT

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ADP5042ACPZ-1 Summary of contents

Page 1

FEATURES Input voltage range: 2 5.5 V One 0.8 A buck regulator Two 300 mA LDOs 20-lead × LFCSP package Initial regulator accuracy: ±1% Overcurrent and thermal protection Soft start Undervoltage lockout Open drain ...

Page 2

ADP5042 TABLE OF CONTENTS Features .............................................................................................. 1 High Level Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 General Specification ................................................................... 3 Supervisory Specification ............................................................ 3 Buck Specifications ....................................................................... 5 LDO1, LDO2 Specifications ....................................................... ...

Page 3

SPECIFICATIONS GENERAL SPECIFICATION AVIN, VIN1 = ( 2.3 V, whichever is greater, AVIN, VIN1 ≥ VIN2, VIN3, T OUT1 are enabled. Table 1. Parameter AVIN UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling SHUTDOWN CURRENT Thermal ...

Page 4

ADP5042 Parameter Watchdog 2 Timeout Period (t ) WD2 Option A Option B Option C Option D Option E Option F Option G Option H Watchdog 2 Power Off Period (t ) POFF Option A Option B WDI1 Pulse Width ...

Page 5

BUCK SPECIFICATIONS AVIN, VIN1 = 3 1 −40°C to +125°C for minimum/maximum specifications µH, C OUT1 J for typical specifications, unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Input Voltage Range ...

Page 6

ADP5042 Parameter Symbol 1 Load Regulation ∆V ∆V 2 DROPOUT VOLTAGE V ACTIVE PULL-DOWN R START-UP TIME T 3 CURRENT-LIMIT THRESHOLD I LIMIT OUTPUT NOISE OUT OUT POWER SUPPLY REJECTION RATIO PSRR 1 Based on an end-point calculation using 1 ...

Page 7

ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVIN, VINx, VOUTx, ENx, MODE WDIx, WMOD, WSTAT, nRSTO to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions ESD Human Body Model ESD Charged Device Model ESD Machine Model Stresses ...

Page 8

ADP5042 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 8. Preliminary Pin Function Descriptions Pin No. Mnemonic Description not connect to this pin. 2 VOUT3 LDO2 Output Voltage and Sensing Input. 3 VIN3 LDO2 Input Supply (1 ...

Page 9

TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = VIN3 = AVIN = 5 VOUT1 1 VOUT2 2 VOUT3 3 B CH1 2.0V/DIV 1MΩ 20.0M A CH1 W B CH2 2.0V/DIV 1MΩ 500M W B CH3 2.0V/DIV 1MΩ 20.0M W ...

Page 10

ADP5042 1.795 1.794 +85°C 1.793 1.792 +25°C 1.791 1.790 1.789 1.788 1.787 1.786 –40°C 1.785 1.784 0 0.1 0.2 0.3 0.4 OUTPUT CURRENT (A) Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode 1.797 1.796 1.795 ...

Page 11

OUTPUT CURRENT (A) Figure 15. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V, PWM Mode 100 –40°C +25°C 90 +85°C 80 ...

Page 12

ADP5042 VOUT CH1 2.0V/DIV 1MΩ 20.0M A CH1 W B CH2 50.0mV/DIV 20. CH3 500mA/DIV 20.0M W Figure 21. Typical Waveforms, VOUT1 = 1.8 V, IOUT2 = 30 mA, Auto Mode ...

Page 13

SW 1 VOUT V 2 OUT LOAD 3 B CH1 4V/DIV 20.0M A CH3 W B CH2 50mV/DIV 20. CH3 50mA/DIV 1MΩ 20.0M W Figure 27. Buck Response to Load Transient, IOUT2 from mA, ...

Page 14

ADP5042 1.53 +85°C +25°C –40°C 1.52 1.51 1.5 1.49 1.48 1.47 0.0001 0.001 0.01 OUTPUT CURRENT (A) Figure 33. LDO1 Load Regulation Across Temperature, VIN2 = 3.3 V, VOUT2 = 1.5 V 1.520 100µA 1mA 10mA 1.515 100mA 150mA 1.510 ...

Page 15

INPUT VOLTAGE (V) Figure 39. LDO2 Ground Current vs. Input Voltage, Across Output Load, VOUT3 = 2.8 V ...

Page 16

ADP5042 100 CH2; V CH2; V CH2; V CH2; V CH2 0.0001 0.001 0.01 0.1 LOAD (mA) Figure 45. LDO1 Output Noise vs. Load Current, Across Input and Output Voltage 100 CH3; VOUT = 3.3V; VIN = 5V ...

Page 17

FREQUENCY (Hz) Figure 51. LDO2 PSRR Across Output Load, VIN3 = 3.1 V, VOUT3 = 2.8 V –10 1mA 10mA ...

Page 18

ADP5042 THEORY OF OPERATION VDDA AVIN GM ERROR PWM COMP VIN1 I LIMIT PWM/ PSM CONTROL LOW BUCK1 CURRENT SW DRIVER AND ANTISHOOT THROUGH PGND POFF MODE MODE ENABLE EN1 ENBK AND MODE CONTROL ENLDO1 EN2 ENLDO2 EN3 SEL VDDA ...

Page 19

Thermal Protection In the event that the junction temperature rises above 150°C, the thermal shutdown circuit turns off the buck and the LDOs. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ...

Page 20

ADP5042 the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% Duty Operation With a dropping input voltage or ...

Page 21

Watchdog 1 Input The ADP5042 features a watchdog timer that monitors micro- processor activity. A timer circuit is cleared with every low-to- high or high-to-low logic transition on the watchdog input pin (WDI1), which detects pulses as short as 80 ...

Page 22

ADP5042 Watchdog Status Indicator In addition to the dual watchdog function, the ADP5042 features a watchdog status monitor available on the WSTAT pin. This pin can be queried by the external processor to determine the origin of a reset. WSTAT ...

Page 23

APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in Figure 66. Inductor The high switching frequency ...

Page 24

ADP5042 The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation RIPPLE π × × × × OUT Capacitors ...

Page 25

Input and Output Capacitor Properties Use any good quality ceramic capacitors with the ADP5042 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior ...

Page 26

ADP5042 using a slightly longer watchdog timeout. In the program that calls the subroutine, WDI1 is set high. The subroutine sets WDI1 low when it is called. If the program executes without error, WDI1 is toggled high and low with ...

Page 27

EVALUATION BOARD SCHEMATICS AND ARTWORK VIN1 = 2.3V TO 5.5V VIN2 = 1.7V TO 5.5V VIN3 = 1.7V TO 5.5V SUGGESTED LAYOUT 0.5 1.0 1.5 GPL 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5 ...

Page 28

ADP5042 BILL OF MATERIAL Table 14. Reference Value C1, C2, C3 µF, X5R, 6 4.7 µF, X5R µF, X5R, 6 Ω FILT L1 1 µH, 0.09 Ω, 290 mA ...

Page 29

FACTORY PROGRAMMABLE OPTIONS Table 15. Reset Voltage Threshold Options Selection 111 (For VIN = 5 V − 6%) 110 (For VOUT = 3.3 V) 101 (For VOUT = 3.3 V) 100 (For VOUT = 2.8 V) 011 (For VOUT = ...

Page 30

... ADP5042 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE Model 1, 2 Regulator Settings ADP5042ACPZ-1-R7 VOUT1 = 1.8 V VOUT2 = 1.5 V VOUT3 = 3.3 V UVLO = 2.2 V Sequencing: LDO1, LDO2, buck ADP5042ACPZ-2-R7 VOUT1 = 1.5 V VOUT2 = 1.8 V VOUT3 = 3.3 V UVLO = 2.2 V Sequencing: LDO1, LDO2, buck ...

Page 31

NOTES Rev Page ADP5042 ...

Page 32

ADP5042 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08811-0-12/10(0) Rev Page ...

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