MM912H634CM1AER2 Freescale Semiconductor, MM912H634CM1AER2 Datasheet - Page 226
MM912H634CM1AER2
Manufacturer Part Number
MM912H634CM1AER2
Description
64KS12 LIN2xLS/HS Isense
Manufacturer
Freescale Semiconductor
Series
-r
Datasheet
1.MM912G634CM1AE.pdf
(345 pages)
Specifications of MM912H634CM1AER2
Applications
Automotive
Core Processor
HCS12
Program Memory Type
FLASH (64 kB)
Controller Series
HCS12
Ram Size
6K x 8
Interface
LIN
Number Of I /o
-
Voltage - Supply
5.5 V ~ 27 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
48-LQFP Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into a range
(COMPA,COMPB configured for range mode). M1 is disabled in range modes.
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry into a range
(COMPA,COMPB configured for range mode)
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding
4.32.5.4
A trigger is generated immediately when one of up to 3 given events occurs
Scenario 3 is possible with S12SDBGV1 SCR encoding
4.32.5.5
Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B and event B must be
followed by event A. 2 consecutive occurrences of event A without an intermediate event B cause a trigger. Similarly 2
consecutive occurrences of event B without an intermediate event A cause a trigger. This is possible by using CompA and
CompC to match on the same address as shown.
Freescale Semiconductor
Scenario 3
Scenario 4
SCR1=0011
SCR3=0001
SCR1=0111
State1
SCR1=0100
State1
SCR1=0010
State1
SCR1=0000
State1
MM912_634 Advance Information, Rev. 4.0
M1
M1
M01
State1
M2
State 3
Figure 70. Scenario 2a
Figure 71. Scenario 2b
Figure 72. Scenario 2c
Figure 74. Scenario 4a
Figure 73. Scenario 3
SCR2=0101
M012
SCR2=0101
SCR2=0011
State2
State2
State2
M2
M0
Final State
M1
M1
M2
M2
M0
Final State
State2
Final State
Final State
Final State
M0
SCR2=0011
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