PIC32MX440F512H-80V/MR Microchip Technology, PIC32MX440F512H-80V/MR Datasheet - Page 102
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PIC32MX440F512H-80V/MR
Manufacturer Part Number
PIC32MX440F512H-80V/MR
Description
512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.TDGL001.pdf
(214 pages)
Specifications of PIC32MX440F512H-80V/MR
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
32 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Operating Temperature Range
- 40 C to + 105 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
PIC32MX3XX/4XX
12.1
All port pins have three registers (TRIS, LAT and
PORT) that are directly associated with their operation.
TRIS is a data direction or tri-state control register that
determines whether a digital pin is an input or an out-
put. Setting a TRISx register bit = 1 configures the cor-
responding I/O pin as an input; setting a TRISx register
bit = 0 configures the corresponding I/O pin as an out-
put. All port I/O pins are defined as inputs after a device
Reset. Certain I/O pins are shared with analog
peripherals and default to analog inputs after a device
Reset.
PORT is a register used to read the current state of the
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx
register, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.
The LATx latch register holds the data written to either
the LATx or PORTx registers. Reading the LATx latch
register
corresponding port or latch register.
Not all port I/O pins are implemented on some devices,
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros.
12.1.1
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
12.1.2
Pins are configured as digital inputs by setting the cor-
responding TRIS register bits = 1. When configured as
inputs, they are either TTL buffers or Schmitt Triggers.
Several digital pins share functionality with analog
inputs and default to the analog inputs at POR. Setting
the corresponding bit in the AD1PCFG register = 1
enables the pin as a digital pin.
DS61143H-page 102
Note:
Parallel I/O (PIO) Ports
reads
CLR, SET AND INV REGISTERS
Using a PORTxINV register to toggle a bit
is recommended because the operation is
performed in hardware atomically, using
fewer instructions as compared to the tra-
ditional read-modify-write method shown
below:
DIGITAL INPUTS
PORTC ^= 0x0001;
the
last
value
written
to
the
The maximum input voltage allowed on the input pins
is the same as the maximum V
Section 29.0 “Electrical Characteristics”
specification details.
12.1.3
Certain pins can be configured as analog inputs used
by the ADC and Comparator modules. Setting the cor-
responding bits in the AD1PCFG register = 0 enables
the pin as an analog input pin and must have the corre-
sponding TRIS bit set = 1 (input). If the TRIS bit is
cleared = 0 (output), the digital output level (V
V
ured as analog, its digital input is disabled and the cor-
responding PORTx register bit will read ‘0’. The
AD1PCFG Register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
12.1.4
Pins are configured as digital outputs by setting the cor-
responding TRIS register bits = 0. When configured as
digital outputs, these pins are CMOS drivers or can be
configured as open drain outputs by setting the corre-
sponding bits in the ODCx Open-Drain Configuration
register.
The open-drain feature allows the generation of
outputs higher than V
tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
See the
and their functionality.
12.1.5
Certain pins can be configured as analog outputs, such
as the CV
module. Configuring the Comparator Reference mod-
ule to provide this output will present the analog output
voltage on the pin, independent of the TRIS register
setting for the corresponding pin.
12.1.6
The input change notification function of the I/O ports
(CNx) allows devices to generate interrupt requests in
response to change of state on selected pin.
Each CNx pin also has a weak pull-up, which acts as a
current source connected to the pin. The pull-ups are
enabled by setting corresponding bit in CNPUE register.
OL
Note:
) will be converted. Any time a port I/O pin is config-
“Pin
REF
Analog levels on any pin that is defined as
a digital input (including the ANx pins)
may cause the input buffer to consume
current that exceeds the device specifica-
tions.
ANALOG INPUTS
DIGITAL OUTPUTS
ANALOG OUTPUTS
INPUT CHANGE NOTIFICATION
Diagrams” section for the available pins
output voltage used by the comparator
IH
specification.
DD
© 2011 Microchip Technology Inc.
(e.g., 5V) on any desired 5V
IH
specification. Refer to
for V
OH
or
IH