N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet
N25Q064A13EF640F
Specifications of N25Q064A13EF640F
Available stocks
Related parts for N25Q064A13EF640F
N25Q064A13EF640F Summary of contents
Page 1
... V, multiple I/O, 4-Kbyte subsector erase, XiP enabled, serial flash memory with 108 MHz SPI bus interface Features SPI-compatible serial bus interface 108 MHz (maximum) clock frequency 2 3.6 V single supply voltage Supports legacy SPI protocol and new Quad I/O or Dual I/O SPI protocol ...
Page 2
Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
N25Q064 - 3 V 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3 Quad SPI (QIO-SPI)Protocol . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
... Program Suspend Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Protection Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Read Identification (RDID Read Data Bytes (READ Read Data Bytes at Higher Speed (FAST_READ Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . . 59 Dual Output Fast Read (DOFR Dual I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Quad Output Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Quad I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Read OTP (ROTP) ...
Page 5
... Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . 85 Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . 86 Multiple I/O Read Identification protocol . . . . . . . . . . . . . . . . . . . . . . . . 89 Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . . 89 Dual Command Fast Read (DCFR Read OTP (ROTP Write Enable (WREN Write Disable (WRDI Dual Command Page Program (DCPP) ...
Page 6
... Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Read Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 102 Write Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . 102 Multiple I/O Read Identification (MIORDID 104 Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . 105 Quad Command Fast Read (QCFR 106 Read OTP (ROTP 108 Write Enable (WREN 109 Write Disable (WRDI) ...
Page 7
N25Q064 - 3 V 10.2 Enter XIP mode by setting the Volatile Configuration Register . . . . . . . 128 10.3 XIP mode hold and exit . . . . . . . . . . . . ...
Page 8
List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
... Write Volatile Enhanced Configuration Register instruction sequence Figure 43. Multiple I/O Read Identification instruction and data-out sequence DIO-SPI . . . . . . . . . . . 89 Figure 44. Dual Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 45. Dual Command Fast Read instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . . 90 Figure 46. Read OTP instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 47 ...
Page 10
... Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI . . . . . . . 102 Figure 70. Multiple I/O Read Identification instruction and data-out sequence QIO-SPI . . . . . . . . . . 105 Figure 71. Quad Read Serial Flash Discovery Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 72. Quad Command Fast Read instruction and data-out sequence QSP, 0Bh . . . . . . . . . . . 107 Figure 73. ...
Page 11
N25Q064 - 3 V Figure 101. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example 129 Figure 102. Power-up ...
Page 12
... Description 1 Description The N25Q064 Mbit (8Mb x 8) multiple I/O high performance serial Flash memory, with advanced security and write protection mechanisms accessed by a high speed SPI-compatible bus with different sets of I/O bus configurations (x1, x2, and x4). It features the possibility to work in XIP (“eXecution in Place”) mode. ...
Page 13
N25Q064 - 3 V The N25Q064 has 64 one-time-programmable bytes (OTP bytes) that can be read and programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP (POTP), respectively. These 64 bytes can be permanently locked by a particular ...
Page 14
Description Figure 2. SO8N, SO8W and MLP8 connections 1. Reset functionality available in devices with a dedicated part number. See information. Figure 3. SO16 connections don’t use. 2. See Package mechanical 3. Reset functionality available in devices ...
Page 15
N25Q064 - Signal descriptions 2.1 Serial data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). When used as ...
Page 16
Signal descriptions 2.5 Hold (HOLD) or Reset (Reset) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. Reset functionality is present instead of Hold in devices with a dedicated part number. ...
Page 17
N25Q064 - 3 V Using the Extended SPI protocol the QIFP, QIEFP and the QIO-SPI Program/Erase instructions still possible to use the VPP additional power supply to speed up internal operations. However, to enable this possibility it is ...
Page 18
SPI Modes 3 SPI Modes These devices can be driven by a micro controller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on ...
Page 19
N25Q064 - parasitic capacitance of the bus line) is shorter than the time during which the bus p master leaves the SPI bus in high impedance. Example pF, that is R*C p master ...
Page 20
SPI Protocols 4 SPI Protocols The N25Q064 memory can work with 3 different Serial protocols: Extended SPI protocol. Dual I/O SPI (DIO-SPI) protocol. Quad I/O SPI (QIO-SPI) protocol possible to choose among the three protocols by means of ...
Page 21
N25Q064 - 3 V 4.3 Quad SPI (QIO-SPI) protocol Quad SPI (QIO-SPI) protocol: instructions, addresses, and I/O data are always transmitted on four data lines DQ0, DQ1, W/VPP(DQ2), and HOLD / (DQ3). The exception is the Program/Erase cycle performed with ...
Page 22
Operating features 5 Operating features 5.1 Extended SPI Protocol Operating features 5.1.1 Read Operations To read the memory content in Extended SPI protocol different instructions are available: READ, Fast Read, Dual Output Fast Read, Dual Input Output Fast Read, Quad ...
Page 23
N25Q064 - 3 V 5.1.5 Quad Input Fast Program The Quad Input Fast Program (QIFP) instruction makes it possible to program up to 256 bytes using 4 input pins at the same time (by changing bits from 1 to 0). ...
Page 24
Operating features When Chip Select (S) is High, the device is deselected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). The device then goes in to the standby power ...
Page 25
N25Q064 - 3 V The Hold/Reset feature can be disabled by using of the bit 4 of the VECR. 5.2 Dual SPI (DIO-SPI) Protocol In the Dual SPI (DIO-SPI) protocol all the instructions, addresses and I/O data are transmitted on ...
Page 26
Operating features The DIO-SPI protocol is similar to the Extended SPI protocol i.e., to program one data byte two instructions are required: Write Enable (WREN), which is one byte, and a Dual Command Page Program (DCPP) sequence, which consists of ...
Page 27
N25Q064 - 3 V 5.3 Quad SPI (QIO-SPI)Protocol In the Quad SPI (QIO-SPI) protocol all the Instructions, addresses and I/O data are transmitted on four data lines, with the exception of the polling instructions performed during a Program or Erase ...
Page 28
Operating features This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Quad Command Page Program (QCPP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to ...
Page 29
N25Q064 - 3 V 5.3.7 Active Power and Standby Power modes Exactly as in Extended SPI protocol, when Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the ...
Page 30
Volatile and Non Volatile Registers 6 Volatile and Non Volatile Registers The device features many different registers to store, in volatile or non volatile mode, many parameters and operating configurations: Legacy SPI Status Register 3 configuration registers: – Non Volatile ...
Page 31
... Each register can be read and modified by means of dedicated instructions in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI). Reading time for all registers is comparable; writing time instead is very different: NVCR bits are set as Flash Cell memory content requiring a longer time to perform internal writing cycles. See Table 31 ...
Page 32
Volatile and Non Volatile Registers Table 2. Status register format 6.1.1 WIP bit The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write Status Register, Program or Erase cycle. 0 indicates no ...
Page 33
N25Q064 - 3 V 6.2 Non Volatile Configuration Register The Non Volatile Configuration Register (NVCR) bits affects the default memory configuration after power-on. It can be used to make the memory start in the configuration to fit the application requirements. ...
Page 34
Volatile and Non Volatile Registers Table 3. Non-Volatile Configuration Register Bit Parameter XIP enabling NVCR<11:9> at POR Output Driver NVCR<8:6> Strength NVCR<5> Reserved Reset/Hold NVCR<4> disable Quad Input NVCR<3> Command Dual Input NVCR<2> Command NVCR<1:0> Reserved 6.2.1 Dummy clock cycle ...
Page 35
N25Q064 - 3 V Dummy Clock All the values are guaranteed by characterization and not 100% tested in production 6.2.2 XIP NV configuration bits (NVCR bits from 11 to ...
Page 36
Volatile and Non Volatile Registers 6.2.5 Quad Input NV configuration bit (NVCR bit 3) The Quad Input NV configuration bit can be used to make the memory start working in QIO- SPI protocol directly after the power on sequence. The ...
Page 37
N25Q064 - 3 V Table 5. Volatile Configuration Register Binary Bit Parameter Value 0000 0001 0010 0011 0100 0101 0110 0111 Dummy VCR<7:4> clock 1000 (1) cycle 1001 1010 1011 1100 1101 1110 1111 0 (2) VCR<3> XIP 1 VCR<2> ...
Page 38
Volatile and Non Volatile Registers clock cycle number, according to cycles) to optimize the fast read instructions performance. Note: If the dummy clock number is not sufficient for the operating frequency, the memory reads wrong data. 6.3.2 XIP Volatile Configuration ...
Page 39
N25Q064 - 3 V Table 7. Volatile Enhanced Configuration Register Bit Parameter Quad Input VECR<7> Command Dual Input VECR<6> Command VECR<5> Reserved Reset/Hold VECR<4> disable Accelerator pin enable in VECR<3> QIO-SPI protocol or in QIFP/QIEFP Output Driver VECR<2:0> Strength 6.4.1 ...
Page 40
Volatile and Non Volatile Registers Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7 and bit 6 of the VECR are set to 0), the memory will work in QIO-SPI. 6.4.3 Reset/Hold disable VECR<4> The ...
Page 41
N25Q064 - 3 V 6.5 Flag Status Register The Flag Status Register is a powerful tool to investigate the status of the device, checking information regarding what is actually doing the memory and detecting possible error conditions. The Flag status ...
Page 42
Volatile and Non Volatile Registers The Erase Suspend Status should be considered valid when the P/E Controller bit is high (FSR<7>=1). When a Program/Erase Resume command (PER) is issued the Erase Suspend Status bit returns Low (FSR<6>=0) 6.5.3 Erase Status ...
Page 43
N25Q064 - 3 V 6.5.5 VPP Status bit The bit 3 of the Flag Status Register represents the VPP Status bit. It indicates an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is sampled ...
Page 44
Protection modes 7 Protection modes There are protocol-related and specific hardware and software protection modes. They are described below. 7.1 SPI Protocol-related protections This applies to all three protocols. The environments where non-volatile memory devices are used can be very ...
Page 45
N25Q064 - 3 V The Lock Registers can be read and written using the Read Lock Register (RDLR) and Write to Lock Register (WRLR) instructions. In each Lock Register two bits control the protection of each sector: the Write Lock ...
Page 46
Protection modes Table 10. Protected area sizes (TB bit = 0) Status Register Content TB bit BP3 Bit BP2 Bit BP1 Bit BP0 Bit ...
Page 47
N25Q064 - Memory organization The memory is organized as: 8,388,608 bytes (8 bits each) 128 sectors (64 Kbytes each) 2,048 subsectors (4 Kbytes each) 32,768 pages (256 bytes each) 64 OTP bytes located outside the main memory ...
Page 48
Memory organization Table 12. Memory organization Sector Subsector 2047 127 2032 2031 126 2016 2015 125 2000 1999 124 1984 1983 123 1968 1967 122 1952 1951 121 1936 1935 120 1920 1919 119 1904 1903 118 1888 1887 117 ...
Page 49
N25Q064 - 3 V Table 12. Memory organization (continued) Sector Subsector 1695 105 1680 1679 104 1664 1663 103 1648 1647 102 1632 1631 101 1616 1615 100 1600 1599 99 1584 1583 98 1568 1567 97 1552 1551 96 ...
Page 50
Memory organization Table 12. Memory organization (continued) Sector Subsector 1343 83 1328 1327 82 1312 1311 81 1296 1295 80 1280 1279 79 1264 1263 78 1248 1247 77 1232 1231 76 1216 1215 75 1200 1199 74 1184 1183 ...
Page 51
N25Q064 - 3 V Table 12. Memory organization (continued) Sector Subsector 991 61 976 975 60 960 959 59 944 943 58 928 927 57 912 911 56 896 895 55 880 879 54 864 863 53 848 847 52 ...
Page 52
Memory organization Table 12. Memory organization (continued) Sector Subsector 639 39 624 623 38 608 607 37 592 591 36 576 575 35 560 559 34 544 543 33 528 527 32 512 511 31 496 495 30 480 479 ...
Page 53
N25Q064 - 3 V Table 12. Memory organization (continued) Sector Subsector 287 17 272 271 16 256 255 15 240 239 14 224 223 13 208 207 12 192 191 11 176 175 10 160 159 9 144 143 8 ...
Page 54
... Register (RFSR), Read NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR), Read Volatile Enhanced Configuration Register (RDVECR), Read Serial Flash Discovery Parameter (RDSFDP), and Read Identification (RDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. ...
Page 55
... Instruction set: extended SPI protocol (page Instruction Description RDID Read Identification READ Read Data Bytes FAST_READ Read Data Bytes at Higher Speed RDSFDP Read Serial Flash Discovery Parameter DOFR Dual Output Fast Read DIOFR Dual Input/Output Fast Read QOFR Quad Output Fast Read One-byte One-byte ...
Page 56
Instructions Table 13. Instruction set: extended SPI protocol (page Instruction Description QIOFR Quad Input/Output Fast Read ROTP Read OTP (Read of OTP area) WREN Write Enable WRDI Write Disable PP Page Program DIFP Dual Input Fast Program ...
Page 57
N25Q064 - 3 V 9.1.1 Read Identification (RDID) The Read Identification (RDID) instruction allows to read the device identification data: – Manufacturer identification (1 byte) – Device identification (2 bytes) – A Unique ID code (UID) (17 bytes, of which ...
Page 58
Instructions Figure 10. Read identification instruction and data-out sequence 9.1.2 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte ...
Page 59
... A23 is “Don’t Care. ” 9.1.4 Read Serial Flash Discovery Parameter The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows reading the Serial Flash Discovery Parameter area (SFDP). This SFDP area is composed of 2048 read-only bytes containing operating characteristics and vendor specific information. The SFDP area is factory programmed. ...
Page 60
... The bytes of SFDP content are shifted out on the Serial Data Output (DQ1) starting from the specified address. Each bit is shifted out during the falling edge of Serial Clock (C). The Read SFDP instruction is terminated by driving Chip Select (S) High at any time during data output. Figure 13. Read Serial Flash Discovery Instruction and Data-out Sequence ...
Page 61
N25Q064 - 3 V The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in ...
Page 62
Instructions Figure 15. Dual I/O Fast Read instruction sequence S Mode Mode 0 Instruction DQ0 DQ1 switches ...
Page 63
N25Q064 - 3 V Note: Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16: Ordering Figure 16. Quad Output Fast Read instruction sequence S Mode Mode ...
Page 64
Instructions Figure 17. Quad Input/ Output Fast Read instruction sequence S Mode Mode 0 Instruction DQ0 Don’t Care DQ1 Don’t Care DQ2 DQ3 ‘1’ *This bit is “Don’t Care. ” 9.1.9 Read OTP (ROTP) ...
Page 65
N25Q064 - 3 V Figure 18. Read OTP instruction and data-out sequence Instruction DQ0 High Impedance DQ1 ...
Page 66
Instructions Figure 19. Write Enable instruction sequence S C DQ0 DQ1 9.1.11 Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, ...
Page 67
N25Q064 - 3 V Figure 20. Write Disable instruction sequence S C DQ0 DQ1 9.1.12 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can ...
Page 68
Instructions Page Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction. Figure 21. Page Program Instruction Sequence Instruction DQ0 ...
Page 69
N25Q064 - 3 V several Dual Input Fast Program (DIFP) sequences each containing only a few bytes. See Table 31.: AC Characteristics. Chip Select (S) must be driven High after the eighth bit of the last data byte has been ...
Page 70
Instructions Figure 23. Dual Input Extended Fast Program instruction sequence S Mode Mode 0 Instruction DQ0 DQ1 ...
Page 71
N25Q064 - 3 V several Quad Input Fast Program (QIFP) sequences each containing only a few bytes See Table 31.: AC Characteristics. Chip Select (S) must be driven High after the eighth bit of the last data byte has been ...
Page 72
Instructions Figure 25. Quad Input Extended Fast Program instruction sequence Instruction DQ0 Don’t Care DQ1 Don’t Care DQ2 DQ3 ‘1’ *Address bit A23 is “Don’t Care. ” 9.1.17 Program OTP instruction (POTP) The Program ...
Page 73
N25Q064 - 3 V Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the OTP memory array become read-only in a permanent way. Any Program OTP (POTP) instruction issued while ...
Page 74
Instructions 9.1.18 Subsector Erase (SSE) The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) ...
Page 75
N25Q064 - 3 V initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the ...
Page 76
Instructions Figure 30. Bulk Erase instruction sequence S C DQ0 9.1.21 Program/Erase Suspend The Program/Erase Suspend instruction allows the controller to interrupt a Program or an Erase instruction, in particular: Sector Erase, Subsector Erase, Page Program, Dual Input Page Program, ...
Page 77
N25Q064 - 3 V Sector Erase or Erase Resume to Erase to Suspend Erase Suspend Program to Program Resume to Program Suspend Suspend SSErase to Sub Sector Erase or Sub Sector Suspend Erase Resume to Erase Suspend Program Sub Sector ...
Page 78
Instructions 9.1.22 Program/Erase Resume After a Program/Erase suspend instruction, a Program/Erase Resume instruction is required to continue performing the suspended Program or Erase sequence. Program/Erase Resume instruction is ignored if the device is not in a Program/Erase Suspended status. The ...
Page 79
N25Q064 - 3 V initiated. While the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 ...
Page 80
Instructions Regardless of the order of the two events, the Hardware Protected mode (HPM) can be entered in either of the following ways: setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W/VPP) Low driving Write Protect ...
Page 81
N25Q064 - 3 V Figure 33. Read Lock Register instruction and data-out sequence Instruction DQ0 High Impedance DQ1 *Address bit A23 is “Don’t Care. ” Table 19. Lock Register out Bit Bit name Value ...
Page 82
Instructions Figure 34. Write to Lock Register instruction sequence Instruction DQ0 *Address bit A23 is “Don’t Care.” Table 20. Lock Register in Sector All sectors 1. Values of (b1, b0) after power-up are ...
Page 83
N25Q064 - 3 V Figure 36. Clear Flag Status Register instruction sequence DQ0 DQ1 9.1.29 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. Figure ...
Page 84
Instructions While the Write Non Volatile Configuration register cycle is in progress possible to monitor the end of the process by polling status Register write in progress (WIP) bit or the Flag Status Register Program/Erase Controller bit. The ...
Page 85
N25Q064 - 3 V 9.1.32 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to the Volatile Configuration register. Before it can be accepted, a write enable (WREN) instruction must have been ...
Page 86
Instructions Figure 41. Read Volatile Enhanced Configuration Register instruction sequence Instruction DQ0 High Impedance DQ1 9.1.34 Write Volatile Enhanced Configuration Register The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new values to ...
Page 87
... Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR), Read Volatile Enhanced Configuration Register (RDVECR), Read Serial Flash Discovery Parameter (RDSFDP), and Multiple I/O Read Identification (MIORDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out ...
Page 88
... Instructions Table 21. Instruction set: DIO-SPI protocol Instruction Description MIORDID Multiple I/O read identification RDSFDP Read Serial Flash Discovery Parameter 01011010 DCFR Dual Command Fast Read ROTP Read OTP WREN Write Enable WRDI Write Disable DCPP Dual Command Page Program POTP Program OTP ...
Page 89
... The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows to read the Serial Flash Discovery Parameter area (SFDP) in the DIO-SPI protocol. The instruction functionality is exactly the same as the Read Serial Flash Discovery Parameter instruction of the Extended SPI protocol; the only difference is that in the DIO- (RDID) ...
Page 90
... SPI protocol instruction code, address and output data are all parallelized on the two pins DQ0 and DQ1. Note: The dummy bits can not be parallelized since these clock cycles are requested to perform the internal reading operation. Figure 44. Dual Read Serial Flash Discovery Parameter ...
Page 91
N25Q064 - 3 V 9.2.4 Read OTP (ROTP) The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the DIO-SPI protocol. The instruction functionality is exactly the same as the Read OTP instruction of the ...
Page 92
Instructions Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write Disable (WRDI) instruction of the Extended SPI protocol, please refer to details. Figure 48. ...
Page 93
N25Q064 - 3 V Figure 50. Dual Command Page Program instruction sequence DSP, A2h Instruction DQ0 DQ1 *Address bit A23 is “Don’t Care. ” Figure ...
Page 94
Instructions Figure 52. Program OTP instruction sequence DIO-SPI Instruction DQ0 DQ1 9.2.9 Subsector Erase (SSE) The Subsector Erase (SSE) instruction sets to '1' (FFh) all ...
Page 95
N25Q064 - 3 V Figure 54. Sector Erase instruction sequence DIO-SPI Instruction DQ0 DQ1 *Address bit A23 is “Don’t Care.” 9.2.11 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before ...
Page 96
Instructions Apart form the parallelizing of the instruction code on the two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Program/Erase Suspend (PES) instruction of the Extended SPI protocol. Figure 56. Program/Erase Suspend instruction sequence ...
Page 97
N25Q064 - 3 V 9.2.14 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the two pins DQ0 and ...
Page 98
Instructions 9.2.16 Read Lock Register (RDLR) The Read Lock Register instructions is used to read the lock register content. Apart form the parallelizing of the instruction code, the address and the output data on the two pins DQ0 and DQ1, ...
Page 99
N25Q064 - 3 V 9.2.18 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the two pins ...
Page 100
Instructions 9.2.20 Read NV Configuration Register The Read Non Volatile Configuration Register (RDNVCR) instruction allows the Non Volatile Configuration Register to be read. Figure 64. Read NV Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.21 Write NV Configuration ...
Page 101
N25Q064 - 3 V 9.2.22 Read Volatile Configuration Register The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile Configuration Register to be read. See Figure 66. Read Volatile Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.23 Write ...
Page 102
Instructions 9.2.24 Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. Figure 68. Read Volatile Enhanced Configuration Register instruction sequence DIO-SPI S C DQ0 DQ1 9.2.25 Write Volatile ...
Page 103
... Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR), Read Volatile Enhanced Configuration Register (RDVECR), Read Serial Flash Discovery Parameter (RDSFDP), and Multiple I/O Read Identification (MIORDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out ...
Page 104
Instructions Table 22. Instruction set: QIO-SPI protocol (page Instruction Description QCPP Quad Command Page Program POTP Program OTP (Program of OTP area) SSE SubSector Erase SE Sector Erase BE Bulk Erase PER Program/Erase Resume PES Program/Erase Suspend ...
Page 105
... The Read Serial Flash Discovery Parameter (RDSFDP) instruction allows reading the Serial Flash Discovery Parameter area (SFDP) in the QIO-SPI protocol. The instruction functionality is exactly the same as the Read Serial Flash Discovery Parameter instruction of the Extended SPI protocol. The only difference is that in the QIO-SPI protocol instruction code, address and output data are all parallelized on the four pins DQ0, DQ1, DQ2 and DQ3 ...
Page 106
... Instructions Figure 71. Quad Read Serial Flash Discovery Parameter S Mode Mode 0 Instruction 4 DQ0 DQ1 5 DQ2 6 DQ3 7* 3 A23-16 A15-8 A7-0 *This bit is “Don’t Care. ” The dummy clock cycle depends on the Fast Read configuration in the NVCR/VCR register (default = 8). 9.3.3 Quad Command Fast Read (QCFR) ...
Page 107
N25Q064 - 3 V Figure 72. Quad Command Fast Read instruction and data-out sequence QSP, 0Bh S Mode Mode 0 Instruction 4 0 DQ0 DQ1 5 1 DQ2 6 2 DQ3 7* 3 A23-16 ...
Page 108
Instructions Figure 74. Quad Command Fast Read instruction and data-out sequence QSP, EBh S Mode Mode 0 Instruction 4 0 DQ0 DQ1 5 1 DQ2 6 2 DQ3 7* 3 A23-16 A15-8 A7-0 *This ...
Page 109
N25Q064 - 3 V Figure 75. Read OTP instruction and data-out sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.5 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Apart form the ...
Page 110
Instructions 9.3.6 Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit. Apart form the parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the ...
Page 111
N25Q064 - 3 V Figure 78. Quad Command Page Program instruction sequence QIO-SPI, 02h S Mode Mode 0 DQ0 DQ1 DQ2 ...
Page 112
Instructions Figure 80. Quad Command Page Program instruction sequence QIO-SPI, 32h S Mode Mode 0 24-bit address* DQ0 DQ1 DQ2 ...
Page 113
N25Q064 - 3 V 9.3.9 Subsector Erase (SSE) The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. Apart form ...
Page 114
Instructions Figure 83. Sector Erase instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 *Address bit A23 is “Don’t Care. ” 9.3.11 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be ...
Page 115
N25Q064 - 3 V suspended and erased while that Subsector Erase, Bulk Erase, Write Non Volatile Configuration register and Program OTP can not be suspended. Apart form parallelizing the instruction code on four pins (DQ0, DQ1, DQ2, DQ3) the instruction ...
Page 116
Instructions Figure 86. Program/Erase Resume instruction sequence QIO-SPI 9.3.14 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. Apart form the parallelizing of the instruction code and the output data on the ...
Page 117
N25Q064 - 3 V 9.3.15 Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. ...
Page 118
Instructions Figure 89. Read Lock Register instruction and data-out sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 *Address bit A23 is “Don’t Care. ” 9.3.17 Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows ...
Page 119
N25Q064 - 3 V Figure 90. Write to Lock Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 *Address bit A23 is “Don’t Care. ” 9.3.18 Read Flag Status Register The Read Flag Status Register (RFSR) instruction allows the ...
Page 120
Instructions Figure 91. Read Flag Status Register instruction sequence QIO-SPI S Mode 3 C Mode 0 Instruction DQ0 DQ1 DQ2 DQ3 9.3.19 Clear Flag Status Register The Clear Flag Status Register (CLFSR) instruction reset the error Flag Status Register bits ...
Page 121
N25Q064 - 3 V Figure 93. Read NV Configuration Register instruction sequence QIO-SPI DQ0 DQ1 DQ2 DQ3 9.3.21 Write NV Configuration Register The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to be written to the Non Volatile ...
Page 122
Instructions Figure 94. Write NV Configuration Register instruction sequence QIO-SPI S C DQ0 DQ1 DQ2 DQ3 9.3.22 Read Volatile Configuration Register The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile Configuration Register to be read. 122/150 ...
Page 123
N25Q064 - 3 V Figure 95. Read Volatile Configuration Register instruction sequence QIO-SPI Instruction DQ0 DQ1 DQ2 DQ3 9.3.23 Write Volatile Configuration Register The Write Volatile Configuration register (WRVCR) instruction allows new values to be written to ...
Page 124
Instructions Figure 96. Write Volatile Configuration Register instruction sequence QIO-SPI DQ0 DQ1 DQ2 DQ3 9.3.24 Read Volatile Enhanced Configuration Register The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the Volatile Configuration Register to be read. Figure 97. Read Volatile ...
Page 125
N25Q064 - 3 V 9.3.25 Write Volatile Enhanced Configuration Register The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new values to be written to the Volatile Enhanced Configuration register. Before it can be accepted, a write enable (WREN) instruction ...
Page 126
... Using the Volatile Configuration Register: this is dedicated to applications that boot in SPI mode (Extended SPI, DIO-SPI or QIO-SPI) and then during the application life need to switch to XIP mode to directly execute some code in the flash. Using the Non Volatile Configuration Register: this is dedicated to applications that need to boot directly in XIP mode ...
Page 127
N25Q064 - 3 V Figure 99. N25Q064 Read functionality Flow Chart Power On NVCR Check No Is XIP enabled ? Yes XIP mode No Yes XiP Confirmation bit = 0 ? 10.1 Enter XIP mode by setting the Non Volatile ...
Page 128
XIP Operations Table 23. NVCR XIP bits setting example default; Quad Figure 100. XIP mode directly after power on NVCR check: XIP enabled Vd t (<100μ) VSI S Mode 3 C Mode 0 DQ0 DQ1 DQ2 DQ3 Xb is the ...
Page 129
N25Q064 - 3 V Then after the next de-select and select cycle (S pin set to 1 and then to 0) the memory codify the first 3 bytes received on the input pin(s) directly as an address, without any instruction ...
Page 130
XIP Operations The device decodes the XIP Confirmation bit with the scheme: XIP Confirmation bit=0 means to hold XIP Mode XIP Confirmation bit=1 means to exit XIP Mode and comes back to read mode, that means codifying the first byte ...
Page 131
N25Q064 - Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC(min) at power-up VSS ...
Page 132
Power-up and power-down Table 25. Power-up timing and V Symbol ( (min) to Read VTR CC ( (min) to device fully accessible VTW CC (1) V Write inhibit voltage WI 1. These parameters are characterized only. ...
Page 133
N25Q064 - Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). Micron Technology, ...
Page 134
Maximum rating 13 Maximum rating Stressing the device outside the ratings listed here may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in ...
Page 135
N25Q064 - and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from ...
Page 136
DC and AC parameters Table 30. DC Characteristics Symbol Parameter ILI Input leakage current ILO Output leakage current ICC1 Standby current Operating current (Fast Read Single I/O) ICC3 Operating current (Fast Read Dual I/O) Operating current (Fast Read Quad I/O) ...
Page 137
N25Q064 - 3 V Table 31. AC Characteristics (page Symbol Alt. tDVCH tDSU Data in setup time tCHDX tDH Data in hold time tCHSH S active hold time (relative to C) tSHCH S not active setup time ...
Page 138
DC and AC parameters Table 31. AC Characteristics (page Symbol Alt. tSSE Subsector erase cycle time Sector Erase Cycle Time tSE Sector Erase Cycle Time Vpp=VPPH Bulk erase cycle time tBE Bulk erase cycle time (with VPP=VPPH) ...
Page 139
N25Q064 - 3 V Table 32. Reset Conditions Symbol Alt. Parameter Reset Recovery (1) tRHSL tREC Time S# deselect to R (1) tSHRV valid 1. All values are guaranteed by characterization and not 100% tested in production. 2. The device ...
Page 140
DC and AC parameters Figure 106. Write protect setup and hold timing during WRSR when SRWD=1 W/V PP tWHSL S C DQ0 DQ1 Figure 107. Hold timing S C DQ1 DQ0 HOLD 140/150 High Impedance tHLCH tCHHL tCHHH tHLQZ Micron ...
Page 141
N25Q064 - 3 V Figure 108. Output timing S C tCLQV tCLQX DQ1 ADDR. DQ0 LSB IN Figure 109. VPP S C DQ0 V PPH V PP tCLQV tCLQX timing H tVPPHSL Micron Technology, Inc., reserves the right to change ...
Page 142
Package mechanical 15 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS compliant packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on ...
Page 143
N25Q064 - 3 V Figure 111. VDFPN8 (MLP8) Very Thin Dual Flat Package No Leads, 8×6x1 mm Drawing A B Ø0 Drawing is not to scale. 2. The circle in the top view of the package indicates ...
Page 144
Package mechanical Table 35. SO8 Wide – 8 Lead Plastic Small Outline, 208 mils Body Width, Dimensions Typ — — — Min 0 1.51 Max 2.50 0.25 2 Figure 113. SO16 Wide – 16 Lead Plastic ...
Page 145
N25Q064 - 3 V Figure 114. TBGA - mm, 24-Ball, Drawing 1. Drawing is not to scale. Package mechanical Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2010 Micron Technology, Inc. ...
Page 146
Package mechanical Table 37. TBGA 6x8 mm 24-Ball, Dimensions, Symbols Typ — 0.20 Min — — Max 1.20 — Table 38. TBGA 6x8 mm 24-Ball, Dimensions, Symbols FD to fff Typ ...
Page 147
... N25Q064 - Ordering information Table 39. Ordering information scheme Example: Device type N25Q = serial Flash memory, Quad I/O, XiP Device density 064 = 064 Mbit Technology Feature set 1 = Byte addressability, Hold pin, Numonyx XiP 2 = Byte addressability, Hold pin, Basic XiP 3 = Byte addressability, Reset pin, Numonyx XiP ...
Page 148
... Valid Order Information Line Items Part Number N25Q064A13E1240E Byte addressability, N25Q064A13E1240F Hold pin, Numonyx XiP N25Q064A13EF640E Byte addressability, N25Q064A13EF640F Hold pin, Numonyx XiP N25Q064A13ESE40F Byte addressability, N25Q064A13ESE40G Hold pin, Numonyx XiP Note: 1 Applies to all part numbers: Packing information details: E= tray, F= tape-n-reel, G= tube (16th digit of part number) ...
Page 149
N25Q064 - Revision history Table 41. Document revision history Date Revision 10-May 2010 22-Oct-2010 19-Nov-2011 1 Initial release. 2 Revised package information. In Ordering Information, changed the following: 3 – Uniform (Uniform 4kB sub-sector erase ...
Page 150
S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data ...