DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 164
DS33R11+
Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS33R11.pdf
(344 pages)
Specifications of DS33R11+
Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
- Current page: 164 of 344
- Download datasheet (12Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE) This bit enables an interrupt if the REPL bit in the
LI.RPPSRL
Bit 6: Receive Aborted Packet Interrupt Enable (RAPIE) This bit enables an interrupt if the RAPL bit in the
LI.RPPSRL register is set.
Bit 5: Receive Invalid Packet Detected Interrupt Enable (RIPDIE) This bit enables an interrupt if the RIPDL bit in
the LI.RPPSRL register is set.
Bit 4: Receive Small Packet Detected Interrupt Enable (RSPDIE) This bit enables an interrupt if the RSPDL bit
in the LI.RPPSRL register is set.
Bit 3: Receive Large Packet Detected Interrupt Enable (RLPDIE) This bit enables an interrupt if the RLPDL bit
in the LI.RPPSRL register is set.
Bit 2: Receive FCS Errored Packet Count Interrupt Enable (REPCIE) This bit enables an interrupt if the REPCL
bit in the LI.RPPSRL register is set. Must be set low when the packets do not have an FCS appended.
Bit 1: Receive Aborted Packet Count Interrupt Enable (RAPCIE) This bit enables an interrupt if the RAPCL bit
in the LI.RPPSRL register is set.
Bit 0: Receive Size Violation Packet Count Interrupt Enable (RSPCIE) This bit enables an interrupt if the
RSPCL bit in the LI.RPPSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
register is set.
REPIE
7
0
RAPIE
6
0
LI.RPPSRIE
Receive Packet Processor Status Register Interrupt Enable
106h
RIPDIE
5
0
RSPDIE
164 of 344
0
4
RLPDIE
3
0
REPCIE
2
0
RAPCIE
1
0
RSPCIE
0
0
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