DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 257
DS33R11+
Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS33R11.pdf
(344 pages)
Specifications of DS33R11+
Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
- Current page: 257 of 344
- Download datasheet (12Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: E1/T1 Select (ETS)
Bit 6: Line Interface Reset (LIRST). Setting this bit from a 0 to a 1 initiates an internal reset that resets the clock
recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on power-up. Must be
cleared and set again for a subsequent reset.
Bit 5: Insert BPV (IBPV). A 0-to-1 transition on this bit causes a single BPV to be inserted into the transmit data
stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three
consecutive 1s to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted.
Bit 4: Transmit Unframed All Ones (TUA1). The polarity of this bit is set such that the device transmits an all-
ones pattern on power-up or device reset. This bit must be set to a 1 to allow the device to transmit data. The
transmission of this data pattern is always timed off of the JACLK.
Bit 3: Jitter Attenuator Mux (JAMUX). Controls the source for JACLK.
Bit 1: Short-Circuit Limit Disable (ETS = 1) (SCLD). Controls the 50mA (RMS) current limiter.
Bit 0: Custom Line Driver Select (CLDS). Setting this bit to a 1 redefines the operation of the transmit line driver.
When this bit is set to a 1 and TR.LIC1.5 = TR.LIC1.6 = TR.LIC1.7 = 0, the device generates a square wave at the
TTIP and TRING outputs instead of a normal waveform. When this bit is set to a 1 and TR.LIC1.5 = TR.LIC1.6 =
TR.LIC1.7 ≠ 0, the device forces TTIP and TRING outputs to become open-drain drivers instead of their normal
push-pull operation. This bit should be set to 0 for normal operation of the device.
0 = T1 mode selected
1 = E1 mode selected
0 = transmit all ones at TTIP and TRING
1 = transmit data normally
0 = JACLK sourced from MCLK (2.048MHz or 1.544MHz at MCLK)
1 = JACLK sourced from internal PLL (2.048MHz at MCLK)
0 = enable 50mA current limiter
1 = disable 50mA current limiter
ETS
7
0
TR.LIC2
Line Interface Control 2
79h
LIRST
6
0
IBPV
5
0
257 of 344
TUA1
0
4
JAMUX
3
0
—
2
0
SCLD
1
0
CLDS
0
0
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