DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 261
DS33R11+
Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS33R11.pdf
(344 pages)
Specifications of DS33R11+
Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
- Current page: 261 of 344
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 – 7: Transmit Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 – 7: Transmit Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 – 7: Transmit Channels 25 to 32 Code Insertion Control Bits (CH25 to CH32)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 – 7: Receive Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8)
0 = do not insert data from the idle-code array into the transmit data stream
1 = insert data from the idle code-array into the transmit data stream
0 = do not insert data from the idle-code array into the transmit data stream
1 = insert data from the idle code-array into the transmit data stream
0 = do not insert data from the idle-code array into the transmit data stream
1 = insert data from the idle-code array into the transmit data stream
0 = do not insert data from the idle-code array into the receive data stream
1 = insert data from the idle-code array into the receive data stream
CH16
CH24
CH32
CH8
7
0
7
0
7
0
7
0
TR.TCICE2
Transmit-Channel Idle-Code Enable Register 2
81h
TR.TCICE3
Transmit-Channel Idle-Code Enable Register 3
82h
TR.TCICE4
Transmit-Channel Idle-Code Enable Register 4
83h
TR.RCICE1
Receive-Channel Idle-Code Enable Register 1
84h
CH15
CH23
CH31
CH7
6
0
6
0
6
0
6
0
CH14
CH22
CH30
CH6
5
0
5
0
5
0
5
0
261 of 344
CH13
CH21
CH29
CH5
0
0
0
0
4
4
4
4
CH20
CH28
CH12
CH4
3
0
3
0
3
0
3
0
CH11
CH19
CH27
CH3
2
0
2
0
2
0
2
0
CH10
CH18
CH26
CH2
1
0
1
0
1
0
1
0
CH17
CH25
CH9
CH1
0
0
0
0
0
0
0
0
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