DS33R11+ Maxim Integrated Products, DS33R11+ Datasheet - Page 72
DS33R11+
Manufacturer Part Number
DS33R11+
Description
IC ETH TXRX T1/E1/J1 256-BGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS33R11.pdf
(344 pages)
Specifications of DS33R11+
Protocol
T1/E1/J1
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
- Current page: 72 of 344
- Download datasheet (12Mb)
10 INTEGRATED T1/E1/J1 TRANSCEIVER
10.1 T1/E1/J1 Clocks
Figure 10-1
shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator,
which can be placed in the receive or transmit path, two are shown for simplification and clarity.
Figure 10-1. T1/E1/J1 Clock Map
The TCLKT MUX is dependent on the state of the TCSS0 and TCSS1 bits in the TR.CCR1 register and the state of
the TCLKT pin.
RXCLK
TXCLK
TO
LIU
MCLKS = 0
RCL = 1
RCL = 0
shows the clock map of the T1/E1 transceiver. The routing for the transmit and receive clocks are
2.048 TO 1.544
SYNTHESIZER
PRE-SCALER
MCLK
LOCAL
LOOPBACK
LLB = 0
LLB = 1
MCLKS = 1
TR.LIC4.MPS0
TR.LIC4.MPS1
TR.LIC2.3
JITTER ATTENUATOR
SEE TR.LIC1
REGISTER
JAS = 0
OR
DJA = 1
JAS = 1
AND
DJA = 0
LTCA
LTCA
JAS = 0
AND
DJA = 0
JAS = 1
OR
DJA = 1
REMOTE
LOOPBACK
RLB = 1
RLB = 0
72 of 344
DJA = 1
DJA = 0
FRAMER
LOOPBACK
FLB = 0
FLB = 1
TRANSMIT
FORMATTER
RECEIVE
FRAMER
8 x PLL
PAYLOAD
LOOPBACK
(SEE NOTES)
PLB = 1
PLB = 0
A
B
BPCLK
SYNTH
C
TCLKT
MUX
TSYSCLK
8XCLK
BPCLK
RCLK
TCLKT
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