DS26324GN+T&R Maxim Integrated Products, DS26324GN+T&R Datasheet - Page 20
DS26324GN+T&R
Manufacturer Part Number
DS26324GN+T&R
Description
IC LIU E1/T1/J1 3.3V 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet
1.DS26324GNTR.pdf
(120 pages)
Specifications of DS26324GN+T&R
Number Of Drivers/receivers
16/16
Protocol
LIN
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figure 5-5. Prescaler PLL and Clock Generator
5.4 Transmitter
NRZ data arrives on TPOS and TNEG on the transmit system side. The TPOS and TNEG data is sampled on the
falling edge of TCLK.
The data is encoded with HDB3 or B8ZS or AMI encoding when single-rail mode is selected (only TPOS as the
data source). When in single-rail mode only, BPV errors can be inserted for test purposes by register BEIR. Pre-
encoded data is expected when dual-rail mode is selected. The encoded data passes through a jitter attenuator if it
is enabled for the transmit path. A digital sequencer and DAC are used to generate transmit waveforms compliant
with T1.102 and G.703 pulse masks.
The line driver supports internal impedance matching for 75Ω, 100Ω, 110Ω, and 120Ω modes.
The DS26324 drivers have short and open circuit driver fail monitor detection. There is an OE pin that can high
impedance the transmitter outputs for protection switching when low. The individual transmitters are by default in
high impedance. The
DS26324 has to have the transmitter’s enabled by setting the register and then pulling the OE pin high. The
registers that control the transmitter operation are shown in
MCLK
MPS1..0
Scaler
PLL
Pre
OE
FREQS
register is used to enable the transmitters individually when the OE pin is high. The
RLCK9..16
RLCK1..8
PLLE
PLLE
T1CLK
E1CLK
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
20 of 120
PCLKS2..0
PCLKS2..0
Table
5-2.
PCLKI1..0
TECLKS
CLKA3..0
GEN
CLK
TECLK
RLOS15
RLOS16
CLKA
TECLKE
CLKAE
LOS16
LOS15
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