DS26324GN+T&R Maxim Integrated Products, DS26324GN+T&R Datasheet - Page 96
DS26324GN+T&R
Manufacturer Part Number
DS26324GN+T&R
Description
IC LIU E1/T1/J1 3.3V 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet
1.DS26324GNTR.pdf
(120 pages)
Specifications of DS26324GN+T&R
Number Of Drivers/receivers
16/16
Protocol
LIN
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 7-2. ID Code Structure
MSB
Version
Contact Factory
4 bits
Table 7-3. Device ID Codes
7.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An
optional test register has been included with the DS26324 design. This test register is the Identification Register
and is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
7.3.1 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells
and is n bits in length.
7.3.2 Bypass Register
This register is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that provide a
short path between TDI and TDO.
7.3.3 Identification Register
The Identification Register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. See
7-2
and
DS26324
DEVICE
Table 7-3
for more information about bit usage.
Device ID
16 bits
16-BIT ID
003Ch
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
JEDEC
00010100001
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LSB
1
1
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