DS26324G+ Maxim Integrated Products, DS26324G+ Datasheet - Page 80
DS26324G+
Manufacturer Part Number
DS26324G+
Description
IC LIU 16CH T1/E1/J1 256CSBGA
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet
1.DS26324GNTR.pdf
(120 pages)
Specifications of DS26324G+
Number Of Drivers/receivers
16/16
Protocol
LIN
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 80 of 120
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address (LIUs 1–8):
Bit #
Name
Default
Register Address (LIUs 9–16):
Bit #
Name
Default
Bits 7 to 0: Line Violation Detect Status n (LVDSn). A bipolar violation, a code violation, or excessive zeros will
cause the associated LVDSn bit to latch. This bit will be cleared on a read operation. The LVDS register captures
the first violation within a three clock period window. If a second violation occurs after the first violation within the
three clock period window, then the second violation will not be latched even if a read to the LVDS register was
performed. Excessive zeros need to be enabled by the
are only relevant when in HDB3 mode and can be disabled for detection by this register by setting the
register.
Register Name:
Register Description:
Register Address (LIUs 1–8):
Bit #
Name
Default
Register Address (LIUs 9–16):
Bit #
Name
Default
Bit 7 to 0: Receive Clock Invert n (RCLKIn). When this bit is set the RCLK for Channel n is inverted. This aligns
RPOS/RNEG on the falling edge of RCLK. When reset or default RPOS/RNEG is aligned on the rising edge of
RCLK.
RCLKI16
LVDS16
RCLKI8
LVDS8
7
0
7
0
7
0
7
0
RCLKI15
LVDS15
RCLKI7
LVDS7
6
0
6
0
6
0
6
0
LVDS
Line Violation Detect Status
12h
32h
RCLKI
Receive Clock Invert
13h
33h
RCLKI14
LVDS14
RCLKI6
LVDS6
5
0
5
0
5
0
5
0
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
RCLKI13
LVDS13
RCLKI5
LVDS5
80 of 120
4
0
4
0
4
0
4
0
EZDE
register for detection by this register. Code violations
RCLKI12
LVDS12
RCLKI4
LVDS4
3
0
3
0
3
0
3
0
RCLKI11
LVDS11
RCLKI3
LVDS3
2
0
2
0
2
0
2
0
RCLKI10
LVDS10
RCLKI2
LVDS2
1
0
1
0
1
0
1
0
RCLKI1
RCLKI9
LVDS1
LVDS9
0
0
0
0
0
0
0
0
CVDEB
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