CY7C68000-56LFXCT Cypress Semiconductor Corp, CY7C68000-56LFXCT Datasheet - Page 12
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CY7C68000-56LFXCT
Manufacturer Part Number
CY7C68000-56LFXCT
Description
IC USB 2.0 TX2 TXRX 56VQFN
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Type
Transceiverr
Datasheet
1.CY7C68000-56LFXC.pdf
(14 pages)
Specifications of CY7C68000-56LFXCT
Protocol
USB 2.0
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Number Of Transceivers
1
Power Supply Requirement
Single
Operating Supply Voltage (typ)
3.3V
Operating Temperature Classification
Commercial
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Document #: 38-08016 Rev. *H
12.0
The following recommendations should be followed to ensure
reliable high-performance operation.
Note:
3.
• At least a four-layer impedance controlled boards are
• Specify impedance targets (ask your board vendor what
• To control impedance, maintain trace widths and trace
• Minimize stubs to minimize reflected signals.
• Connections between the USB connector shell and signal
required to maintain signal quality.
they can achieve).
spacing to within specifications.
ground must be done near the USB connector.
Source for recommendations: EZ-USB FX2™ PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf High-
Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
CORNER
PIN #1
E-PAD maximum size
4.75 X 5.46 mm [187 x 215 mils] (width x length).
PCB Layout Recommendations
A
DIMENSIONS IN MM[INCHES] MIN.
REFERENCE JEDEC MO-220
Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 x 8 mm) (SAWN VERSION)
TOP VIEW
7.90[0.311]
8.10[0.319]
MAX.
56-Lead QFN 8 x 8 mm (Sawn Version) LS56B
1.00[0.039] MAX.
[3]
SIDE VIEW
C
0.08[0.003]
• Bypass/flyback capacitors on VBus, near the connector, are
• DPLUS and DMINUS trace lengths should be kept to within
• Maintain a solid ground plane under the DPLUS and
• If possible, do not place any vias on the DPLUS or DMINUS
• Isolate the DPLUS and DMINUS traces from all other signal
0.04[0.0015] MAX.
0.20[0.008] REF.
SEATING
PLANE
recommended.
2 mm of each other in length, with preferred length of 20–30
mm.
DMINUS traces. Do not allow the plane to be split under
these traces.
trace routing.
traces by no less than 10 mm.
C
0.50[0.020]
0.30[0.012]
6.45[0.254]
6.55[0.258]
(PAD SIZE VARY
BY DEVICE TYPE)
0.28[0.011]
0.18[0.007]
BOTTOM VIEW
E-PAD
0.50[0.020]
CY7C68000
51-85187-*A
Page 12 of 14
CORNER
PIN #1
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