ST90T158M9Q6 STMicroelectronics, ST90T158M9Q6 Datasheet
ST90T158M9Q6
Specifications of ST90T158M9Q6
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ST90T158M9Q6 Summary of contents
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UP TO 64K ROM/OTP/EPROM AND RAM Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW and HALT modes MHz Operation @ 5V 10%, - +85 C and ...
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GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Divide by Zero trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PORT ...
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Clocks And Serial Transmission Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 ...
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ST90158 - GENERAL DESCRIPTION 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST90158 and ST90135 microcontrollers are developed and manufactured by STMicroelectron- ics using a proprietary n-well CMOS process. Their performance derives from the use of a flexi- ble 256-register programming model ...
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Multifunction Timers (MFT) Each multifunction timer has a 16-bit Up/Down counter supported by two 16-bit Compare regis- ters and two 16-bit input capture registers. Timing resolution can be programmed using an 8-bit pres- caler. Multibyte transfers between the peripheral ...
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ST90158 - GENERAL DESCRIPTION Figure 1. ST90158 Block Diagram EPROM/ ROM/ Kbytes RAM Kbytes AS WAIT 256 bytes NMI Register File R/W DS 8/16 bits CPU Interrupt Management INT0-7 ST9+ CORE OSCIN OSCOUT ...
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Figure 2. ST90135 Block Diagram ROM Kbytes RAM Kbyte AS WAIT 256 bytes NMI Register File R/W DS 8/16 bits CPU Interrupt Management INT0-7 ST9+ CORE OSCIN OSCOUT RESET RCCU INTCLK CKAF WDIN WDOUT ...
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ST90158 - GENERAL DESCRIPTION 1.2 PIN DESCRIPTION AS: Address Strobe (output, active low, 3-state). Address Strobe is pulsed low once at the begin- ning of each memory cycle. The rising edge of AS indicates that address, Read/Write (R/W), and Data ...
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PIN DESCRIPTION (Cont’d) Figure 3. 80-Pin TQFP Pin-out 80 AD6/P0 AD7/P0 P4.0 P4.1 INTCLK/P4.2 STOUT/P4.3 WDOUT/I NT0/P4.4 INT4/P4.5 T0OUTB/INT5 /P4.6 T0OUTA/P4.7 P2.0 P2.1 P2.2 P2.3 20 P2.4 21 ST90158 - ...
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ST90158 - GENERAL DESCRIPTION PIN DESCRIPTION (Cont’d) Figure 4. 80-Pin PQFP Pin-Out 80 1 AD4/P0.4 AD5/P0.5 AD6/P0 AD7/P0 P4.0 P4.1 INTCLK/P4.2 STOUT/P4.3 INT0/WDOUT/P4.4 INT4/P4.5 INT5/T0OUTB/P4.6 T0OUTA/P4.7 P2.0 P2.1 P2.2 P2.3 P2.4 ...
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I/O PORT PINS All the ports of the device can be programmed as Input/Output or in Input mode, compatible with TTL or CMOS levels (except where Schmitt Trig- ger is present). Each bit can be programmed indi- vidually (Refer ...
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ST90158 - GENERAL DESCRIPTION I/O PORT PINS (Cont’d) How to Configure the I/O ports To configure the I/O ports, use the information in Table 1, Table 2 and the Port Bit Configuration Ta- ble in the I/O ports Chapter (See ...
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Pin No. Port General Purpose I/O Name P1 A11 P1 A12 P1 A13 P1 A14 P1 A15 P2.4 ...
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ST90158 - GENERAL DESCRIPTION Pin No. Port General Purpose I/O Name R/W P6 AIN0 RX0CKIN P7 WDIN EXTRG AIN1 P7.1 31 ...
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Pin No. Port General Purpose I/O Name P9 S1OUT T0OUTB P9 S1IN CLK1OUT O SCI1 Byte Sync Clock output P9 TX1CKIN All ports useable for general pur- S0OUT P9.4 pose I/O (input ...
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ST90158 - DEVICE ARCHITECTURE 2 DEVICE ARCHITECTURE 2.1 CORE ARCHITECTURE The ST9+ Core or Central Processing Unit (CPU) features a highly optimised instruction set, capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean ...
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MEMORY SPACES (Cont’d) Figure 6. Register Groups 255 F PAGED REGISTERS 240 239 E SYSTEM REGISTERS 224 223 Figure 8. Addressing the Register ...
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ST90158 - DEVICE ARCHITECTURE MEMORY SPACES (Cont’d) 2.2.2 Register Addressing Register File registers, including Group F paged registers (but excluding Group D), may be ad- dressed explicitly by means of a decimal, hexa- decimal or binary address; thus R231, RE7h ...
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SYSTEM REGISTERS The System registers are listed in Table 4. They are used to perform all the important system set- tings. Their purpose is described in the following pages. Refer to the chapter dealing with I/O for a description ...
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ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) 2.3.2 Flag Register The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the ...
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SYSTEM REGISTERS (Cont’d) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include a Sdm instruction. Note that ...
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ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) 7 RG4 RG3 RG2 RG1 RG0 RPS Bit 7:3 = RG[4:0]: Register Group number. These bits contain ...
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SYSTEM REGISTERS (Cont’d) Figure 9. Pointing to a single group of 16 registers REGISTER BLOCK GROUP NUMBER REGIST ER FILE r15 ...
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ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) 2.3.4 Paged Registers pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always ...
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SYSTEM REGISTERS (Cont’d) DS, R/W) can be forced into the High Impedance state by setting the HIMP bit. When this bit is reset, it has no effect. Setting the HIMP bit is recommended for noise re- duction when only internal ...
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ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) USER STACK POINTER HIGH REGISTER (USPHR) R236 - Read/Write Register Group: E (System) Reset value: undefined 7 USP1 USP1 USP1 USP1 USP1 USP1 USER STACK POINTER LOW ...
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MEMORY ORGANIZATION Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a common address space. The ...
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ST90158 - DEVICE ARCHITECTURE 2.5 MEMORY MANAGEMENT UNIT The CPU Core includes a Memory Management Unit (MMU) which must be programmed to per- form memory accesses (even if external memory is not used). The MMU is controlled by 7 registers ...
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ADDRESS SPACE EXTENSION To manage 4 Mbytes of addressing space it is necessary to have 22 address bits. The MMU adds 6 bits to the usual 16-bit address, thus trans- lating a 16-bit virtual address into a 22-bit physical ...
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ST90158 - DEVICE ARCHITECTURE ADDRESS SPACE EXTENSION (Cont’d) 2.6.2 Addressing 64-Kbyte Segments This extension mode is used to address Data memory space during a DMA and Program mem- ory space during any code execution (normal code and interrupt routines). Three ...
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MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. 7 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 ...
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ST90158 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) 2.7.2 CSR: Code Segment Register This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if the spm instruc- tion has ...
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MMU REGISTERS (Cont’d) Figure 16. Memory Addressing Scheme (example) DPR3 DPR2 DPR1 DPR0 DMASR ISR CSR 9 ST90158 - DEVICE ARCHITECTURE 4M bytes 3FFFFFh 16K 294000h 240000h 23FFFFh 20C000h 16K 200000h 16K 1FFFFFh 040000h 03FFFFh 64K 030000h 020000h 64K 010000h ...
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ST90158 - DEVICE ARCHITECTURE 2.8 MMU USAGE 2.8.1 Normal Program Execution Program memory is organized as a set of 64- Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries. jps, ...
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... Apart from this case no other part of the Program memory has a predeter- mined function except segment 21h which is re- served for use by STMicroelectronics. 3.2 EPROM PROGRAMMING The 65536 bytes of EPROM memory of the ST90E158 may be programmed by using the EPROM Programming Boards (EPB) or gang pro- grammers available from STMicroelectronics ...
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ST90158 - REGISTER AND MEMORY MAP Figure 17. Interrupt Vector Table REGISTE R FILE F PAGE REGISTE RS INT. VECTOR REGISTER R240 R239 38/190 9 PROGRAM MEMORY USER ISR USER DIVIDE-BY -ZERO ISR USER MAIN PROGRAM USER TOP LEVEL ISR ...
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MEMORY MAP Figure 18. Memory Map 20FFFFh Internal RAM 512 bytes 20FE00h 768 bytes 20FD00h 1 Kbytes 20FC00h 1.5 Kbytes 20FA00h 2 Kbytes 20F800h 00FFFFh 64 Kbytes 00BFFFh 48 Kbytes 007FFFh 32 Kbytes 24 Kbytes 00FFFFh 003FFFh Internal ROM ...
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ST90158 - REGISTER AND MEMORY MAP 3.4 ST90158/135 REGISTER MAP The following pages contain a list of ST90158/135 registers, grouped by peripheral or function. Table 6. Common Registers Function or Peripheral SCI, MFT ADC SPI, WDT, STIM I/O PORTS EXTERNAL ...
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Table 7. Group F Pages Resources available on the ST90158/ST90135 devices: Register R255 Res. R254 PORT SPI 7 R253 Res. R252 WCR R251 R250 PORT WDT 6 PORT R249 2 R248 MFT1 R247 Res. Res. R246 ...
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ST90158 - REGISTER AND MEMORY MAP Table 8. Detailed Register Map Page Reg. Register Block No. Name (Decimal) R230 CICR R231 FLAGR R232 RP0 R233 RP1 R234 PPR Core R235 MODER R236 USPHR N/A R237 USPLR R238 SSPHR R239 SSPLR ...
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Page Reg. Register Block No. Name (Decimal) R240 P4C0 I/O Port R241 P4C1 4 R242 P4C2 R244 P5C0 I/O Port R245 P5C1 5 R246 P5C2 R248 P6C0 3 I/O R249 P6C1 Port R250 P6C2 6 R251 P6DR R252 P7C0 I/O ...
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ST90158 - REGISTER AND MEMORY MAP Page Reg. Register Block No. Name (Decimal) R240 REG0HR1 R241 REG0LR1 R242 REG1HR1 R243 REG1LR1 R244 CMP0HR1 R245 CMP0LR1 R246 CMP1HR1 R247 CMP1LR1 8 R248 TCR1 R249 TMR1 MFT1 R250 ICR1 R251 PRSR1 R252 ...
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Page Reg. Register Block No. Name (Decimal) R240 STH R241 STL 11 STIM R242 STP R243 STC R240 REG0HR1 R241 REG0LR1 R242 REG1HR1 R243 REG1LR1 R244 CMP0HR1 R245 CMP0LR1 R246 CMP1HR1 R247 CMP1LR1 12 R248 TCR1 R249 TMR1 MFT3 R250 ...
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ST90158 - REGISTER AND MEMORY MAP Page Reg. Register Block No. Name (Decimal) R240 RDCPR0 R241 RDAPR0 R242 TDCPR0 R243 TDAPR0 R244 IVR0 R245 ACR0 R246 IMR0 R247 ISR0 24 SCI0 R248 RXBR0 R248 TXBR0 R249 IDPR0 R250 CHCR0 R251 ...
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Page Reg. Register Block No. Name (Decimal) R240 CLKCTL 55 RCCU R242 CLK_FLAG R246 PLLCONF R240 D0R0 R241 D1R0 R242 D2R0 R243 D3R0 R244 D4R0 R245 D5R0 R246 D6R0 R247 D7R0 63 AD0 R248 LT6R0 R249 LT7R0 R250 UT6R0 R251 ...
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ST90158 - INTERRUPTS 4 INTERRUPTS 4.1 INTRODUCTION The ST9 responds to peripheral and external events through its interrupt channels. Current pro- gram execution can be suspended to allow the ST9 to execute a specific response routine when such an event ...
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Segment Paging During Routines The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compati- bility mode and ST9+ interrupt management mode. ST9 backward compatibility mode (ENCSR = 0) If ENCSR is reset, ...
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ST90158 - INTERRUPTS with the highest position in the chain, as shown in Figure 9 Table 9. Daisy Chain Priority Highest Position INTA0 INT0/WDT INTA1 INT1 INTB0 INT2/SPI INTB1 INT3 INTC0 INT4/STIM INTC1 INT5 INTD0 INT6/RCCU INTD1 INT7 TIMER0 SCI0 ...
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ARBITRATION MODES (Cont’d) Examples In the following two examples, three interrupt re- quests with different priority levels (2, 3 & 4) occur simultaneously during the interrupt 5 service rou- tine. Figure 21. Simple Example of a Sequence of Interrupt Requests ...
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ST90158 - INTERRUPTS ARBITRATION MODES (Cont’d) Example 2 In the second example, (more complex, Figure 22), each interrupt service routine sets Interrupt Enable with the ei instruction at the beginning of the routine. Placed here, it minimizes response time for ...
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ARBITRATION MODES (Cont’d) 4.5.2 Nested Mode The difference between Nested mode and Con- current mode, lies in the modification of the Cur- rent Priority Level (CPL) during interrupt process- ing. The arbitration phase is basically identical to Con- current mode, ...
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ST90158 - INTERRUPTS ARBITRATION MODES (Cont’d) End of Interrupt Routine The iret Interrupt Return instruction executes the following steps: – The Flag register is popped from system stack. – If ENCSR is set, CSR is popped from system stack. – ...
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EXTERNAL INTERRUPTS The standard ST9 core contains 8 external inter- rupts sources grouped into four pairs. Table 10. External Interrupt Channel Grouping External Interrupt Channel INT7 INTD1 INT6 INTD0 INT5 INTC1 INT4 INTC0 INT3 INTB1 INT2 INTB0 INT1 INTA1 ...
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ST90158 - INTERRUPTS EXTERNAL INTERRUPTS (Cont’d) Figure 26. External Interrupts Control Bits and Vectors n Watchdog/Timer IA0S End of count TEA0 “0” “1” INT 0 pin * INT 1 pin SPEN,BM S TEB0 SPI Interrupt “0,0” INT 2 pin * ...
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TOP LEVEL INTERRUPT The Top Level Interrupt channel can be assigned either to the external pin NMI or to the Timer/ Watchdog according to the status of the control bit EIVR.TLIS (R246.2, Page 0). If this bit is high ...
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ST90158 - INTERRUPTS 4.9 INTERRUPT RESPONSE TIME The interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. One more CPUCLK cycle is required when an interrupt is acknowledged. Requests are sampled every 5 CPUCLK ...
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INTERRUPT REGISTERS CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h) 7 GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 Bit 7 = GCEN: Global Counter Enable. This bit enables the 16-bit ...
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ST90158 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) 7 IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 Bit 7 = IPD1: INTD1 Interrupt Pending bit Bit 6 = ...
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INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110b (x6h TLTEV TLIS IAOS EWEN Bit 7:4 = V[7:4]: Most significant nibble of External Interrupt Vector . ...
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ST90158 - INTERRUPTS INTERRUPT REGISTERS (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0000 1111 (0Fh ENCSR Bit 7, 5:0 = Reserved, keep in reset state. Refer to ...
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ON-CHIP DIRECT MEMORY ACCESS (DMA) 5.1 INTRODUCTION The ST9 includes on-chip Direct Memory Access (DMA) in order to provide high-speed data transfer between peripherals and memory or Register File. Multi-channel DMA is fully supported by peripher- als having their ...
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ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA) 5.3 DMA TRANSACTIONS The purpose of an on-chip DMA channel is to transfer a block of data between a peripheral and the Register File, or Memory. Each DMA transfer consists of three operations: ...
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DMA TRANSACTIONS (Cont’d) When selecting the DMA transaction with memory, bit DCPR.RM (bit 0 of DCPR) must be cleared. To select between using the ISR or the DMASR reg- ister to extend the address, (see Memory Manage- ment Unit chapter), ...
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ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA) DMA TRANSACTIONS (Cont’d) 5.4 DMA CYCLE TIME The interrupt and DMA arbitration protocol func- tions completely asynchronously from instruction flow. Requests are sampled every 5 CPUCLK cycles. DMA transactions are executed if their ...
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DMA REGISTERS As each peripheral DMA channel has its own spe- cific control registers, the following register list should be considered as a general example. The names and register bit allocations shown here may be different from those found ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) 6 RESET AND CLOCK CONTROL UNIT (RCCU) 6.1 INTRODUCTION The Reset and Clock Control Unit (RCCU) com- prises two distinct sections: – the Clock Control Unit, which generates and manages the internal ...
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CLOCK MANAGEMENT The various programmable features and operating modes of the CCU are handled by four registers: – MODER (Mode Register) This is a System Register (R235, Group E). The input clock divide-by-two and the CPU clock prescaler factors ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK MANAGEMENT (Cont’d) 6.3.1 PLL Clock Multiplier Programming The CLOCK1 signal generated by the oscillator drives a programmable divide-by-two circuit. If the DIV2 control bit in MODER is set (Reset Condi- tion), ...
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CLOCK MANAGEMENT (Cont’d) 6.3.4 Low Power Modes The user can select an automatic slowdown of clock frequency during Wait for Interrupt opera- tion, thus idling in low power mode while waiting for an interrupt. In WFI operation the clock to ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) Figure 34. Example of Low Power mode programming in WFI using CK_AF external clock PROGRAM FLOW Begin MX(1:0) DX2-0 WAIT CSU_CKSEL WFI_CKSEL XTSTOP LPOWFI User’s Program WFI instruction WFI status Interrupt Interrupt ...
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Figure 35. Example of Low Power mode programming in WFI using CLOCK2/16 PROGRAM FLOW Begin MX(1:0) 01 DX2-0 000 WAIT CSU_CKSEL LPOWFI 1 User’s Program WFI instruction WFI status Interrupt Interrupt Routine WAIT CSU_CKSEL User’s Program 9 ST90158 - RESET ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) 6.4 CLOCK CONTROL REGISTERS MODE REGISTER (MODER) R235 - Read/Write System Register Reset Value: 1110 0000 (E0h DIV2 PRS2 PRS1 PRS0 *Note: This register contains bits which relate to ...
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CLOCK CONTROL REGISTERS (Cont’d) CLOCK FLAG REGISTER (CLK_FLAG) R242 -Read/Write Register Page: 55 Reset Value: 0100 10x0 after a Watchdog Reset Reset Value: 0010 10x0 after a Software Reset Reset Value: 0000 10x0 after a Power-On Reset 7 EX_ WDGRE ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK CONTROL REGISTERS (Cont’d) PLL CONFIGURATION REGISTER (PLLCONF) R246 - Read/Write Register Page: 55 Reset Value: xx00 x111 MX1 MX0 - DX2 Bit 5:4 = MX[1:0]: PLL Multiplication Factor ...
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OSCILLATOR CHARACTERISTICS The on-chip oscillator circuit uses an inverting gate circuit with tri-state output. Notes recommended to place the quartz or crystal as close as possible to the ST9 to reduce the parasitic capacitance. At low temperature, ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) OSCILLATOR CHARACTERISTICS (Cont’d) CERAMIC RESONATORS Murata Electronics CERALOCK resonators have been tested with the ST90158 at 3, 3.68, 4 and 5 MHz. Some resonators have built-in capacitors (see Table 18). The test ...
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RESET/STOP MANAGER The Reset/Stop Manager resets the MCU when one of the three following events occurs: – A Hardware reset, initiated by a low level on the RESET pin. – A Software reset, initiated by a HALT instruction (when ...
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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) RESET/STOP MANAGER (Cont’d) The on-chip Timer/Watchdog generates a reset condition if the Watchdog mode is enabled (WCR.WDEN cleared, R252 page 0), and if the programmed period elapses without the specific code (AAh, ...
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EXTERNAL MEMORY INTERFACE (EXTMI) 7.1 INTRODUCTION The ST9 External Memory Interface uses two reg- isters (EMR1 and EMR2) to configure external memory accesses. Some interface signals are also affected by WCR - R252 Page 0. If the two registers ...
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ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) 7.2 EXTERNAL MEMORY SIGNALS The access to external memory is made using the AS, DS, DS2, RW, Port 0, Port1, and WAIT signals described below. Refer to Figure 45 7.2.1 AS: Address Strobe AS ...
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EXTERNAL MEMORY SIGNALS (Cont’d) Figure 44. Effects of DS2EN on the behavior of DS and DS2 n SYSTEM CLOCK AS (MC=0) DS2EN=0 OR (DS2EN=1 AND UPPER MEMORY ADDRESSED): DS (MC=0) DS (MC=1, READ) DS (MC=1, WRITE) DS2 DS2EN=1 AND LOWER ...
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ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) Figure 45. External memory Read/Write with a programmable wait n NO WAIT CYCLE T1 T2 SYSTEM CLOCK AS (MC=0) ALE (MC=1) P1 ADDRESS DS (MC=0) P0 ADDRESS DATA IN MULTIPLEXED ...
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EXTERNAL MEMORY SIGNALS (Cont’d) 7.2.4 RW: Read/Write RW (Alternate Function Output, Active low, Tristate) identifies the type of memory cycle: RW=”1” identifies a memory read cycle, RW=”0” identifies a memory write cycle defined at the beginning of each ...
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ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) EXTERNAL MEMORY SIGNALS (Cont’d) Whenever it is sampled low, the System Clock is stretched and the external memory signals (AS, DS, DS2, RW, P0 and P1) are released in high-im- pedance. The external memory ...
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REGISTER DESCRIPTION EXTERNAL MEMORY REGISTER 1 (EMR1) R245 - Read/Write Register Page: 21 Reset value: 1000 0000 (80h DS2EN ASAF x ETO Bit 7 = Reserved. Bit 6 = MC: Mode Control . 0: AS, DS ...
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ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) REGISTER DESCRIPTION (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0000 1111 (0Fh) 7 MEM - ENCSR DPRREM LAS1 LAS0 UAS1 UAS0 SEL Bit 7 = Reserved. Bit ...
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REGISTER DESCRIPTION (Cont’d) Bit 1:0 = UAS[1:0]: Upper memory address strobe stretch . These two bits contain the number of wait cycles (from add to the System Clock to stretch AS during external upper memory block ...
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ST90158 - I/O PORTS 8 I/O PORTS 8.1 INTRODUCTION ST9 devices feature flexible individually program- mable multifunctional input/output lines. Refer to the Pin Description Chapter for specific pin alloca- tions. These lines, which are logically grouped as 8-bit ports, can ...
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PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 and 1 in ROM- ...
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ST90158 - I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 49. Control Bits Bit 7 PxC2 PxC27 PxC1 PxC17 PxC0 PxC07 n Table 19. Port Bit Configuration Table ( 1... port number) PXC2n 0 1 PXC1n ...
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INPUT/OUTPUT BIT CONFIGURATION (Cont’d) Figure 50. Basic Structure of an I/O Port Pin PUSH-PULL TRISTATE OPEN DRAIN WEAK PULL-UP OUTPUT SLAVE LATCH ALTERNATE FROM FUNCTION PERIPHERAL OUTPUT INPUT OUTPUT BIDIRECTIONAL OUTPUT MASTER LATCH Figure 51. Input Configuration I/O PIN TRISTATE ...
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ST90158 - I/O PORTS INPUT/OUTPUT BIT CONFIGURATION (Cont’d) When Px.n is programmed as an Output: (Figure 52) – The Output Buffer is turned Open-drain or Push-pull configuration. – The data stored in the Output Master Latch is ...
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ALTERNATE FUNCTION ARCHITECTURE Each I/O pin may be connected to three different types of internal signal: – Data bus Input/Output – Alternate Function Input – Alternate Function Output 8.5.1 Pin Declared as I/O A pin declared as I/O, is ...
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ST90158 - TIMER/WATCHDOG (WDT) 9 ON-CHIP PERIPHERALS 9.1 TIMER/WATCHDOG (WDT) Important Note: This chapter is a generic descrip- tion of the WDT peripheral. However depending on the ST9 device, some or all of WDT interface signals described may not be ...
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TIMER/WATCHDOG (Cont’d) 9.1.2 Functional Description 9.1.2.1 External Signals The HW0SW1 pin can be used to permanently en- able Watchdog mode. Refer to Section 0.1.3.1. The WDIN Input pin can be used in one of four modes: – Event Counter Mode ...
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ST90158 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 9.1.2.7 Gated Input Mode This mode can be used for pulse width measure- ment. The Timer is clocked by INTCLK/4, and is started and stopped by means of the input pin and the ST_SP ...
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TIMER/WATCHDOG (Cont’d) 9.1.3.3 Preventing Watchdog System Reset In order to prevent a system reset, the sequence AAh, 55h must be written to WDTLR (Watchdog Timer Low Register). Once 55h has been written, the Timer reloads the constant and counting re- ...
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ST90158 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) 9.1.4 WDT Interrupts The Timer/Watchdog issues an interrupt request at every End of Count, when this feature is ena- bled. A pair of control bits, IA0S (EIVR.1, Interrupt A0 se- lection bit) and TLIS ...
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TIMER/WATCHDOG (Cont’d) 9.1.5 Register Description The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR: Timer/Watchdog High Register WDTLR: Timer/Watchdog Low Register WDTPR: Timer/Watchdog Prescaler Register WDTCR: Timer/Watchdog Control Register Three additional ...
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ST90158 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) Bit 3 = INEN: Input Enable . This bit is set and cleared by software. 0: Disable input section 1: Enable input section Bit 2 = OUTMD: Output Mode. This bit is set and ...
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MULTIFUNCTION TIMER (MFT) 9.2.1 Introduction The Multifunction Timer (MFT) peripheral offers powerful timing capabilities and features 12 oper- ating modes, including automatic PWM generation and frequency measurement. The MFT comprises a 16-bit Up/Down counter driven by an 8-bit programmable ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) The configuration of each input is programmed in the Input Control Register. Each of the two output pins can be driven from any of three possible sources: – Compare Register 0 logic ...
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MULTIFUNCTION TIMER (Cont’d) 9.2.2 Functional Description The MFT operating modes are selected by pro- gramming the Timer Control Register (TCR) and the Timer Mode Register (TMR). 9.2.2.1 Trigger Events A trigger event may be generated by software (by setting either ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 9.2.2.8 Free Running Mode The timer counts continuously ( down mode) and the counter value simply overflows or underflows through FFFFh or zero; there is no End Of Count condition ...
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MULTIFUNCTION TIMER (Cont’d) Every software or external trigger event on REG0R performs a reload from REG0R resetting the Biload cycle. In One Shot mode (reload initiat software external trigger), reloading is always from REG0R. B) ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 9.2.3 Input Pin Assignment The two external inputs (TxINA and TxINB) of the timer can be individually configured to catch a par- ticular external event (i.e. rising edge, falling edge, or both ...
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MULTIFUNCTION TIMER (Cont’d) 9.2.3.1 TxINA = I/O - TxINB = I/O Input pins A and B are not used by the Timer. The counter clock is internally generated and the up/ down selection may be made only by software via ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 9.2.3.9 TxINA = Clock Up - TxINB = Clock Down The edge received on input pin A (or B) performs a one step up (or down) count, so that the counter clock ...
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MULTIFUNCTION TIMER (Cont’d) 9.2.3.13 Autodiscrimination Mode The phase between two pulses (respectively on in- put pin B and input pin A) generates a one step up (or down) count, so that the up/down control and the counter clock are both ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 9.2.4 Output Pin Assignment Two external outputs are available when pro- grammed as Alternate Function Outputs of the I/O pins. Two registers Output A Control Register (OACR) and Output B Control Register ...
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MULTIFUNCTION TIMER (Cont’d) For a configuration where TxOUTA is driven by the Over/Underflow and by Compare 0, and TxOUTB is driven by the Over/Underflow and by Compare 1. OACR is programmed with TxOUTA preset to “0”. OUF sets TxOUTA while ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 9.2.5 Interrupt and DMA 9.2.5.1 Timer Interrupt The timer has 5 different Interrupt sources, be- longing to 3 independent groups, which are as- signed to the following Interrupt vectors: Table 23. Timer ...
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MULTIFUNCTION TIMER (Cont’d) Figure 62. Pointer Mapping for Register to Register Transfers Register File 8 bit Counter XXXXXX11 8 bit Addr Pointer XXXXXX10 8 bit Counter XXXXXX01 8 bit Addr Pointer XXXXXX00 9.2.5.4 DMA Transaction Priorities Each Timer DMA transaction ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) 9.2.5.6 DMA End Of Block Interrupt Routine An interrupt request is generated after each block transfer (EOB) and its priority is the same as that assigned in the usual interrupt request, for ...
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MULTIFUNCTION TIMER (Cont’d) CAPTURE LOAD 0 HIGH REGISTER (REG0HR) R240 - Read/Write Register Page: 10 Reset value: undefined 7 R15 R14 R13 R12 R11 R10 This register is used to capture values from the Up/Down counter or load preset values ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) TIMER CONTROL REGISTER (TCR) R248 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 CCP CCMP UDC CEN CCL UDC Bit 7 = CEN: Counter enable . ...
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MULTIFUNCTION TIMER (Cont’d) TIMER MODE REGISTER (TMR) R249 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 OE1 OE0 BM RM1 RM0 ECK REN Bit 7 = OE1: Output 1 enable. 0: Disable the Output 1 (TxOUTB pin) ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) EXTERNAL INPUT CONTROL (T_ICR) R250 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 IN3 IN2 IN1 IN0 A0 A1 Bit 7:4 = IN[3:0]: Input pin function. These bits are ...
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MULTIFUNCTION TIMER (Cont’d) OUTPUT A CONTROL REGISTER (OACR) R252 - Read/Write Register Page: 10 Reset value: 0000 0000 7 C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 CEV 0P Note: Whenever more than one event occurs si- multaneously, the action taken will ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) OUTPUT B CONTROL REGISTER (OBCR) R253 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 OEV 0P Note: Whenever more than one event occurs ...
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MULTIFUNCTION TIMER (Cont’d) FLAG REGISTER (T_FLAGR) R254 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 OCP CP0 CP1 CM0 CM1 OUF 0 Bit 7 = CP0: Capture 0 flag. This bit is set by hardware after a ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA MASK REGISTER (IDMR) R255 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) 7 GT- CM0 CP0D CP0I CP1I CM0I CM1I OUI IEN D Bit 7 = GTIEN: Global timer ...
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MULTIFUNCTION TIMER (Cont’d) DMA ADDRESS POINTER REGISTER (DAPR) R241 - Read/Write Register Page: 9 Reset value: undefined 7 DAP DAP DAP5 DAP4 DAP3 DAP2 7 6 Bit 7:2 = DAP[7:2]: MSB of DMA address register location. These are the most ...
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ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA CONTROL REGISTER (IDCR) R243 - Read/Write Register Page: 9 Reset value: 1100 0111 (C7h) 7 DCT SWE CPE CME DCTS PL2 D N Bit 7 = CPE: Capture 0 EOB . ...
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STANDARD TIMER (STIM) Important Note: This chapter is a generic descrip- tion of the STIM peripheral. Depending on the ST9 device, some or all of the interface signals de- scribed may not be connected to external pins. For the ...
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ST90158 - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 9.3.2 Functional Description 9.3.2.1 Timer/Counter control Start-stop Count. The ST-SP bit (STC.7) is used in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer ...
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STANDARD TIMER (Cont’d) 9.3.2.4 Standard Timer Output Modes OUTPUT modes are selected using 2 bits of the STC register: OUTMD1 and OUTMD2. No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”) The output is disabled and the corresponding pin is ...
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ST90158 - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d) 9.3.5 Register Description COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) 7 ST.15 ST.14 ST.13 ST.12 ST.11 ST.10 ST.9 ST.8 Bit 7:0 = ST.[15:8]: ...
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SERIAL PERIPHERAL INTERFACE (SPI) 9.4.1 Introduction The Serial Peripheral Interface (SPI general purpose on-chip shift register peripheral. It allows communication with external peripherals via an SPI protocol bus. In addition, special operating modes allow re- duced software ...
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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 9.4.3 Functional Description The SPI, when enabled, receives input data from the internal data bus to the SPI Data Register (SPIDR). A Serial Clock (SCK) is generated by controlling through ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 66. SPI I/O Pins n SCK SDO SDI PORT BIT LATCH PORT BIT LATCH PORT BIT LATCH INT2 ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) 9.4.4 Interrupt Structure The SPI peripheral is associated with external in- ...
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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 9.4.5 Working With Other Protocols The SPI peripheral offers the following facilities for 2 operation with S-bus/I C-bus and IM-bus proto- cols: Interrupt request on start/stop detection Hardware clock synchronisation ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 2 Table 26. Typical I C-bus Sequences Phase Software SPICR.CPOL, CPHA = 0, 0 SPICR.SPEN = 0 SPICR.BMS = 1 INITIALIZE SCK pin set as AF output SDI pin set as input Set SDO port bit ...
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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) The data on the SDA line is sampled on the low to high transition of the SCL line. SPI working with an I2C-bus 2 To use the SPI with the ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 9.4.7 S-Bus Interface The S-bus is a three-wire bidirectional data-bus, possessing functional features similar to the I 2 bus. As opposed to the I C-bus, the Start/Stop conditions are determined by encoding the infor- mation on ...
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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) 9.4.8 IM-bus Interface The IM-bus features a bidirectional data line and a clock line; in addition, it requires an IDENT line to distinguish an address byte from a data byte ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 9.4.9 Register Description It is possible to have independent SPIs in the same device (refer to the device block dia- gram). In this case they are named SPI0 thru SPI2. If the device ...
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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d) Bit 2 = CPHA: Transmission Clock Phase. CPHA controls the relationship between the data on the SDI and SDO pins, and the clock signal on the SCK pin. The CPHA ...
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SERIAL COMMUNICATIONS INTERFACE (SCI) 9.5.1 Introduction The Serial Communications Interface (SCI) offers full-duplex serial data exchange with a wide range of external equipment. The SCI offers four operat- ing modes: Asynchronous, Asynchronous with synchronous clock, Serial expansion and Syn- ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.5.2 Functional Description The SCI offers four operating modes: – Asynchronous mode – Asynchronous mode with synchronous clock – Serial expansion mode – Synchronous mode Figure 76. SCI Functional Schematic ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.5.3 SCI Operating Modes 9.5.3.1 Asynchronous Mode In this mode, data and clock can be asynchronous (the transmitter and receiver can use their own clocks to sample received data), each data bit is sampled 16 times ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.5.3.3 Serial Expansion Mode This mode is used to communicate with an exter- nal synchronous peripheral. The transmitter only provides the clock waveform during the period that data is being ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 78. SCI Operating Modes START BIT DATA I CLOCK Asynchronous Mode I/O DATA START BIT (Dummy) CLOCK Serial Expansion Mode Note: In all operating modes, the Least Significant Bit is transmitted/received first. ST90158 ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.5.4 Serial Frame Format Characters sent or received by the SCI can have some or all of the features in the following format, depending on the operating mode: START: the ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.5.4.1 Data transfer Data to be transmitted by the SCI is first loaded by the program into the Transmitter Buffer Register. The SCI will transfer the data into the Transmitter Shift Register when the Shift Register ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 80. Auto Echo Configuration TRANSMITTE R RECEIVER All modes except Synchronous Figure 81. Loop Back Configuration LOGICAL 1 TRANSMITT ER RECEIVER All modes except Synchronous Figure 82. Auto Echo ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.5.5 Clocks And Serial Transmission Rates The communication bit rate of the SCI transmitter and receiver sections can be provided from the in- ternal Baud Rate Generator or from external sources. The bit rate clock is ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 28. SCI Baud Rate Generator Divider Values Example 1 Baud Clock Desired Freq Rate Factor (kHz) 50. 0.80000 75. 1.20000 110. 1.76000 300.00 ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.5.7 Input Signals SIN: Serial Data Input. This pin is the serial data input to the SCI receiver shift register. TXCLK: External Transmitter Clock Input. This pin is the external input clock driving the SCI trans- ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.5.9 Interrupts and DMA 9.5.9.1 Interrupts The SCI can generate interrupts as a result of sev- eral conditions. Receiver interrupts include data pending, receive errors (overrun, framing and par- ity), ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 31. SCI Interrupt Vectors Interrupt Source Transmitter Buffer or Shift Register Empty Transmit DMA end of Block Received Data Pending Receive DMA end of Block Break Detector Address Word Match Receiver Error Figure 85. SCI ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.5.9.2 DMA Two DMA channels are associated with the SCI, for transmit and for receive. These follow the reg- ister scheme as described in the DMA chapter. DMA Reception To ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 9.5.10 Register Description The SCI registers are located in the following pag the ST9: SCI number 0: page 24 (18h) SCI number 1: page 25 (19h) (when present) The SCI is controlled by the ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER DMA COUNTER POINTER (RDCPR) R240 - Read/Write Reset value: undefined 7 RC7 RC6 RC5 RC4 RC3 RC2 Bit 7:1 = RC[7:1]: Receiver DMA Counter Pointer. These bits contain the ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT VECTOR REGISTER (S_IVR) R244 - Read/Write Reset value: undefined EV2 Bit 7:3 = V[7:3]: SCI Interrupt Vector Base Ad- dress. User programmable interrupt vector bits for trans- mitter and ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT MASK REGISTER (IMR) R246 - Read/Write Reset value: 0xx00000 7 BSN RXEOB TXEOB RXE RXA RXB Bit 7 = BSN: Buffer or shift register empty inter- rupt . This ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT STATUS REGISTER (S_ISR) R247 - Read/Write Reset value: undefined RXAP RXBP RXDP Bit 7 = OE: Overrun Error Pending . This bit is set by hardware if the data in the ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER BUFFER REGISTER (RXBR) R248 - Read only Reset value: undefined 7 RD7 RD6 RD5 RD4 RD3 RD2 Bit 7:0 = RD[7:0]: Received Data. This register stores the data portion ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT/DMA PRIORITY REGISTER (IDPR) R249 - Read/Write Reset value: undefined 7 AMEN SB SA RXD TXD PRL2 Bit 7 = AMEN: Address Mode Enable. This bit, together with the AM bit (in the CHCR reg- ister), ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) CHARACTER CONFIGURATION (CHCR) R250 - Read/Write Reset value: undefined PEN AB SB1 SB0 Bit 7 = AM: Address Mode . This bit, together with the AMEN bit ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CLOCK CONFIGURATION REGISTER (CCR) R251 - Read/Write Reset value: 0000 0000 (00h) 7 XTCLK OCLK XRX XBRG CD AEN Bit 7 = XTCLK This bit, together with the OCLK bit, selects the source for the transmitter ...
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ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) BAUD RATE GENERATOR HIGH REGISTER (BRGHR) R252 - Read/Write Reset value: undefined 15 BG15 BG14 BG13 BG12 BG11 BG10 BAUD RATE GENERATOR LOW REGISTER (BRGLR) R253 - Read/Write Reset value: ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) SYNCHRONOUS OUTPUT CONTROL (SOCR) R255 - Read/Write Reset value: 0000 0001 (01h) 7 OUTP OUTS OCKP OCKS RTSE RTS Bit 7 = OUTPL: SOUT Output Polarity. 0: Polarity not inverted. ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) 9.6 EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) 9.6.1 Introduction The 8-Channel Analog to Digital Converter (A/D) comprises an input multiplex channel selector feeding a successive approximation converter. Conversion requires 138 INTCLK cycles ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) Single and continuous conversion modes are available. Conversion may be triggered by an ex- ternal signal or, internally, by the Multifunction Timer. A Power-Down programmable bit allows ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) Analog channels 6 and 7 monitor an acceptable voltage level window for the converted analog in- puts. The external voltages applied to inputs 6 and 7 are ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) Figure 88. Application Example: Analog Watchdog used in Motorspeed Control n 9.6.3 Interrupts The A/D provides two interrupt sources: – End of Conversion – Analog Watchdog Request ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) 9.6.4 Register Description DATA REGISTERS (DiR) The conversion results for the 8 available chan- nels are loaded into the 8 Data registers following conversion of the corresponding ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) CHANNEL 6 LOWER THRESHOLD REGISTER (LT6R) R248 - Read/Write Register Page: 63 Reset Value: undefined 7 LT6.7 LT6.6 LT6.5 LT6.4 LT6.3 LT6.2 LT6.1 LT6.0 Bit 7:0 = ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) CONTROL LOGIC REGISTER (CLR) The Control Logic Register (CLR) manages the A/D converter logic. Writing to this register will cause the current conversion to be aborted and ...
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ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) INTERRUPT CONTROL REGISTER (AD_ICR) R254 - Read/Write Register Page: 63 Reset Value: 0000 1111 (0Fh) 7 ECV AWD ECI AWDI X PL2 Bit 7 = ECV: End ...
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ST90158 - ELECTRICAL CHARACTERISTICS 10 ELECTRICAL CHARACTERISTICS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the ...
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DC ELECTRICAL CHARACTERISTICS ( 10 - unless otherwise specified Symbol Parameter V Clock Input High Level IHCK V Clock Input Low Level ILCK V Input High Level IH V Input ...
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ST90158 - ELECTRICAL CHARACTERISTICS AC TEST CONDITIONS AC ELECTRICAL CHARACTERISTICS ( 10 - INTCLK = 16 MHz unless otherwise specified Symbol Parameter I Run Mode Current, PLL on DDRUN I ...
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EXTERNAL BUS TIMING TABLE ( 10 - Cload = 50pF, INTCLK = 16MHz, unless otherwise specified Symbol 1 TsA (AS) Address Set-up Time before AS 2 ThAS (A) Address ...
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ST90158 - ELECTRICAL CHARACTERISTICS EXTERNAL BUS TIMING 178/190 9 ...
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EXTERNAL INTERRUPT TIMING TABLE ( 10 -40 C +85 C, Cload = 50pF, INTCLK = 12MHz, Push-pull output configuration, un less otherwise specified) N Symbol Parameter Low Level Minimum Pulse Width in 1 TwLR ...
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ST90158 - ELECTRICAL CHARACTERISTICS SPI TIMING TABLE ( 10 - Cload = 50pF, INTCLK = 12MHz, Output Alternate Function set Push-pull) N Symbol 1 TsDI Input Data Set-up Time ...
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WATCHDOG TIMING TABLE ( 10 - Cload = 50pF, INTCLK = 12MHz, Push-pull output configuration unless otherwise specified ) N Symbol 1 TwWDOL WDOUT Low Pulse Width 2 TwWDOH WDOUT ...
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ST90158 - ELECTRICAL CHARACTERISTICS A/D EXTERNAL TRIGGER TIMING TABLE N Symbol Parameter 1 Tw External trigger pulse width LOW 2 Tw External trigger pulse distance HIGH External trigger active edges 3 Tw EXT distance (1) EXTRG falling edge and first ...
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A/D INTERNAL TRIGGER TIMING TABLE N Symbol Parameter Internal trigger 1 Tw HIGH pulse width Internal trigger 2 Tw LOW pulse distance Internal trigger 3 Tw active edges EXT distance (1) Internal delay between INTRG 4 Tw STR rising edge ...
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ST90158 - ELECTRICAL CHARACTERISTICS A/D CHANNEL ENABLE TIMING TABLE N Symbol Parameter 1 Tw CEn Pulse width (1) EXT Notes number of autoscanned channels (1 < n < Variable clock (Tpc = OSCIN clock period) ...
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A/D ANALOG SPECIFICATIONS (VDD = 4.5V TO 5.0 V) Parameter Conversion time Sample time Power-up time Resolution Monotonicity No missing codes Zero input reading Full scale reading Offset error Gain error Diff. Non Linearity Int. Non Linearity Absolute Accuracy A ...
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ST90158 - ELECTRICAL CHARACTERISTICS MULTIFUNCTION TIMER UNIT EXTERNAL TIMING TABLE N Symbol Parameter 1 Tw External clock/trigger pulse width CTW 2 Tw External clock/trigger pulse distance CTD 3 Tw Distance between two active edges AED 4 Tw Gate pulse width ...
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SCI TIMING TABLE ( 10 +85 C, Cload = 50pF, INTCLK = 12MHz, Output Alternate Function set Push-pull) N Symbol Parameter F Frequency of RxCKIN RxCKIN Tw RxCKIN shortest ...
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ST90158 - GENERAL INFORMATION 11 GENERAL INFORMATION 11.1 PACKAGE MECHANICAL DATA Figure 89. 80-Pin Thin Plastic Quad Flat Package 11.2 80-PIN PLASTIC QUAD FLAT PACKAGE 188/190 1 mm 0.10mm Dim .004 Min Typ Max seating plane A A1 0.05 A2 ...
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... ST90135M4Q6 16K ROM ST90135M5Q6 24K ROM ST90135M6Q6 32K ROM ST90158M7Q6 48K ROM ST90158M9Q6 64K ROM ST90158M9T1 ST90E158M9G0 64K EPROM ST90E158M9LVG0 ST90T158M9Q6 ST90T158M9LVQ1 64K OTP ST90T158M9LVT1 ST90R158Q6 ROMless ST90R158T1 ROMless 9 ST90158 - GENERAL INFORMATION Dim Min 0.30 0.35 0.45 0.012 0.014 0.018 C 0 ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...