ST92F120V1Q7 STMicroelectronics, ST92F120V1Q7 Datasheet - Page 113

• Manufacturer Part Number: ST92F120V1Q7
• Description: Microcontrollers (MCU) Flash 128K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST92F120V1Q7

• Data Bus Width: 8 bit, 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 16 Channel
• Lead Free Status / Rohs Status: No

EXTERNAL MEMORY SIGNALS (Cont’d)
8.2.4 RW: Read/Write
RW (Alternate Function Output, Active low,
Tristate) identifies the type of memory cycle:
RW=”1” identifies a memory read cycle, RW=”0”
identifies a memory write cycle. It is defined at the
beginning of each memory cycle and it remains
stable until the following memory cycle. RW is re-
leased in high-impedance during bus acknowl-
edge cycle or under processor control by setting
the HIMP bit (MODER). RW is enabled via soft-
ware as the Alternate Function output of the asso-
ciated I/O port bit (refer to specific ST9 device to
identify the port and pin). Under Reset status, the
associated bit of the port is set into bidirectional
weak pull-up mode.
n
n
Figure 59. External Memory Read/Write Sequence with External Wait (WAIT pin)
n
MULTIPLEXED
MULTIPLEXED
ALE (MC=1)
RW (MC=0)
RW (MC=1)
DS (MC=0)
DS (MC=1)
AS (MC=0)
RW (MC=0)
RW (MC=1)
DS (MC=1)
SYSTEM
CLOCK
WAIT
P0
P0
P1
ADD.
ADD.
T1
ADDRESS
D.OUT
D.IN
T2
ST92F120 - EXTERNAL MEMORY INTERFACE (EXTMI)
ADDRESS
T1
ADDRESS
ADDRESS
The behavior of this signal is affected by the MC,
ETO and BSZ bits in the EMR1 register. Refer to
the Register description.
8.2.5
Acknowledge
Note: These pins are available only on some ST9
devices (see Pin description).
BREQ (Alternate Function Input, Active low) indi-
cates to the ST9 that a bus request has tried or is
trying to gain control of the memory bus. Once en-
abled by setting the BRQEN bit (MODER.1,
R235), BREQ is sampled with the falling edge of
the processor internal clock during phase T2.
D.OUT
D.IN
T2
BREQ,
ADD.
T1
ADD.
BACK:
ADDRESS
Bus
T2
DATA OUT
Request,
D.IN
113/324
Bus
9